intc: nxp_s32: use instance-based DT macros
At present, many of the NXP S32 shim drivers do not make use of devicetree instance-based macros because the NXP S32 HAL relies on an index-based approach, requiring knowledge of the peripheral instance index during both compilation and runtime, and this index might not align with the devicetree instance index. The proposed solution in this patch eliminates this limitation by determining the peripheral instance index during compilation through macrobatics. Note that for some peripheral instances is needed to define the HAL macros of the peripheral base address because there are gaps in the instances or there are SoCs with a single instance. Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit is contained in:
Manuel Argüelles
Anas Nashif
parent
c777ef255b
commit
237ec65ad3
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@ -4,6 +4,8 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_s32_siul2_eirq
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#include <zephyr/irq.h>
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#include <zephyr/sys/sys_io.h>
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#include <zephyr/drivers/pinctrl.h>
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@ -124,23 +126,17 @@ static int eirq_nxp_s32_init(const struct device *dev)
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return 0;
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}
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#define EIRQ_NXP_S32_NODE(n) DT_NODELABEL(eirq##n)
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#define EIRQ_NXP_S32_CALLBACK(line, n) \
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void nxp_s32_icu_##n##_eirq_line_##line##_callback(void) \
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{ \
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const struct device *dev = DEVICE_DT_GET(EIRQ_NXP_S32_NODE(n)); \
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\
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eirq_nxp_s32_callback(dev, line); \
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eirq_nxp_s32_callback(DEVICE_DT_INST_GET(n), line); \
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}
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#define EIRQ_NXP_S32_CHANNEL_CONFIG(idx, n) \
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{ \
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.hwChannel = idx, \
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.digFilterEn = DT_PROP_OR(DT_CHILD(EIRQ_NXP_S32_NODE(n), line_##idx), \
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filter_enable, 0), \
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.maxFilterCnt = DT_PROP_OR(DT_CHILD(EIRQ_NXP_S32_NODE(n), line_##idx), \
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filter_counter, 0), \
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.digFilterEn = DT_INST_PROP_OR(DT_CHILD(n, line_##idx), filter_enable, 0), \
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.maxFilterCnt = DT_INST_PROP_OR(DT_CHILD(n, line_##idx), filter_counter, 0), \
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.intSel = SIUL2_ICU_IRQ, \
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.intEdgeSel = SIUL2_ICU_DISABLE, \
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.callback = NULL, \
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@ -155,8 +151,7 @@ static int eirq_nxp_s32_init(const struct device *dev)
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#define EIRQ_NXP_S32_INSTANCE_CONFIG(n) \
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static const Siul2_Icu_Ip_InstanceConfigType eirq_##n##_instance_nxp_s32_cfg = { \
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.intFilterClk = DT_PROP_OR(EIRQ_NXP_S32_NODE(n), \
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filter_prescaler, (0)), \
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.intFilterClk = DT_INST_PROP_OR(n, filter_prescaler, 0), \
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.altIntFilterClk = 0U, \
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}
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@ -176,42 +171,45 @@ static int eirq_nxp_s32_init(const struct device *dev)
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#define _EIRQ_NXP_S32_IRQ_NAME(name) DT_CAT3(SIUL2_EXT_IRQ_, name, _ISR)
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#define EIRQ_NXP_S32_IRQ_NAME(idx, n) \
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COND_CODE_1(DT_NODE_HAS_PROP(EIRQ_NXP_S32_NODE(n), interrupt_names), \
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(_EIRQ_NXP_S32_IRQ_NAME( \
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DT_STRING_TOKEN_BY_IDX(EIRQ_NXP_S32_NODE(n), interrupt_names, idx))), \
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COND_CODE_1(DT_INST_NODE_HAS_PROP(n, interrupt_names), \
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(_EIRQ_NXP_S32_IRQ_NAME(DT_INST_STRING_TOKEN_BY_IDX(n, interrupt_names, idx))), \
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(DT_CAT3(SIUL2_, n, _ICU_EIRQ_SINGLE_INT_HANDLER)))
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#define _EIRQ_NXP_S32_IRQ_CONFIG(idx, n) \
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do { \
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IRQ_CONNECT(DT_IRQ_BY_IDX(EIRQ_NXP_S32_NODE(n), idx, irq), \
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DT_IRQ_BY_IDX(EIRQ_NXP_S32_NODE(n), idx, priority), \
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IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, idx, irq), \
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DT_INST_IRQ_BY_IDX(n, idx, priority), \
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EIRQ_NXP_S32_IRQ_NAME(idx, n), \
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DEVICE_DT_GET(EIRQ_NXP_S32_NODE(n)), \
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COND_CODE_1(CONFIG_GIC, \
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(DT_IRQ_BY_IDX(EIRQ_NXP_S32_NODE(n), idx, flags)), \
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(0))); \
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irq_enable(DT_IRQ_BY_IDX(EIRQ_NXP_S32_NODE(n), idx, irq)); \
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DEVICE_DT_INST_GET(n), \
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COND_CODE_1(CONFIG_GIC, (DT_INST_IRQ_BY_IDX(n, idx, flags)), (0))); \
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irq_enable(DT_INST_IRQ_BY_IDX(n, idx, irq)); \
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} while (false);
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#define EIRQ_NXP_S32_IRQ_CONFIG(n) \
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LISTIFY(DT_NUM_IRQS(EIRQ_NXP_S32_NODE(n)), _EIRQ_NXP_S32_IRQ_CONFIG, (), n)
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LISTIFY(DT_NUM_IRQS(DT_DRV_INST(n)), _EIRQ_NXP_S32_IRQ_CONFIG, (), n)
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#define EIRQ_NXP_S32_HW_INSTANCE_CHECK(i, n) \
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(((DT_REG_ADDR(DT_INST_PARENT(n))) == IP_SIUL2_##i##_BASE) ? i : 0)
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#define EIRQ_NXP_S32_HW_INSTANCE(n) \
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LISTIFY(__DEBRACKET SIUL2_INSTANCE_COUNT, EIRQ_NXP_S32_HW_INSTANCE_CHECK, (|), n)
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#define EIRQ_NXP_S32_INIT_DEVICE(n) \
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EIRQ_NXP_S32_CONFIG(n) \
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PINCTRL_DT_DEFINE(EIRQ_NXP_S32_NODE(n)); \
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PINCTRL_DT_INST_DEFINE(n); \
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static const struct eirq_nxp_s32_config eirq_nxp_s32_conf_##n = { \
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.instance = n, \
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.disr0 = (mem_addr_t)DT_REG_ADDR_BY_NAME(EIRQ_NXP_S32_NODE(n), disr0), \
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.direr0 = (mem_addr_t)DT_REG_ADDR_BY_NAME(EIRQ_NXP_S32_NODE(n), direr0), \
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.instance = EIRQ_NXP_S32_HW_INSTANCE(n), \
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.disr0 = (mem_addr_t)DT_INST_REG_ADDR_BY_NAME(n, disr0), \
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.direr0 = (mem_addr_t)DT_INST_REG_ADDR_BY_NAME(n, direr0), \
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.icu_cfg = (Siul2_Icu_Ip_ConfigType *)&eirq_##n##_nxp_s32_cfg, \
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.pincfg = PINCTRL_DT_DEV_CONFIG_GET(EIRQ_NXP_S32_NODE(n)) \
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.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n) \
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}; \
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static struct eirq_nxp_s32_cb eirq_nxp_s32_cb_##n[NXP_S32_NUM_CHANNELS]; \
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static struct eirq_nxp_s32_data eirq_nxp_s32_data_##n = { \
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.cb = eirq_nxp_s32_cb_##n, \
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}; \
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static int eirq_nxp_s32_init##n(const struct device *dev); \
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DEVICE_DT_DEFINE(EIRQ_NXP_S32_NODE(n), \
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DEVICE_DT_INST_DEFINE(n, \
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eirq_nxp_s32_init##n, \
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NULL, \
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&eirq_nxp_s32_data_##n, \
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@ -233,18 +231,4 @@ static int eirq_nxp_s32_init(const struct device *dev)
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return 0; \
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}
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#if DT_NODE_HAS_STATUS(EIRQ_NXP_S32_NODE(0), okay)
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EIRQ_NXP_S32_INIT_DEVICE(0)
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#endif
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#if DT_NODE_HAS_STATUS(EIRQ_NXP_S32_NODE(1), okay)
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EIRQ_NXP_S32_INIT_DEVICE(1)
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#endif
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#if DT_NODE_HAS_STATUS(EIRQ_NXP_S32_NODE(4), okay)
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EIRQ_NXP_S32_INIT_DEVICE(4)
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#endif
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#if DT_NODE_HAS_STATUS(EIRQ_NXP_S32_NODE(5), okay)
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EIRQ_NXP_S32_INIT_DEVICE(5)
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#endif
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DT_INST_FOREACH_STATUS_OKAY(EIRQ_NXP_S32_INIT_DEVICE)
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@ -18,4 +18,9 @@
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#undef FALSE
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#endif
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/* Aliases for peripheral base addresses */
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/* SIUL2 */
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#define IP_SIUL2_0_BASE IP_SIUL2_BASE
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#endif /* _NXP_S32_S32K_SOC_H_ */
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@ -1,5 +1,5 @@
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/*
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* Copyright 2022 NXP
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* Copyright 2022-2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -10,4 +10,9 @@
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/* Do not let CMSIS to handle GIC */
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#define __GIC_PRESENT 0
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/* Aliases for peripheral base addresses */
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/* SIUL2 */
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#define IP_SIUL2_2_BASE 0U /* instance does not exist on this SoC */
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#endif /* _NXP_S32_S32ZE_SOC_H_ */
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