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dts: intel_s1000: enable DTS for GPIO

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Added GPIO to SoC device tree
Updated SoC DTS fixup
Removed Kconfig variables now replaced by DT

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
This commit is contained in:
Sathish Kuttan 2018-11-23 21:49:38 -08:00 committed by Anas Nashif
parent 212b2180c9
commit 23f11933b9
4 changed files with 31 additions and 10 deletions
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5
boards/xtensa/intel_s1000_crb/Kconfig.defconfig
View file

@ -46,11 +46,6 @@ config CAVS_ISR_TBL_OFFSET
config DW_ISR_TBL_OFFSET
default 3RD_LVL_ISR_TBL_OFFSET
config GPIO_DW_0_NAME
default "GPIO_PORTA"
config GPIO_DW_0_IRQ_PRI
default 1
config I2C_0_DEFAULT_CFG
default 0x12
if DMA_CAVS

12
dts/xtensa/intel_s1000.dtsi
View file

@ -1,5 +1,6 @@
#include "skeleton.dtsi"
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/gpio.h>
/ {
cpus {
@ -84,6 +85,17 @@
interrupt-parent = <&cavs0>;
};
gpio0: gpio@80c00 {
compatible = "snps,designware-gpio";
reg = <0x00080c00 0x400>;
bits = <32>;
label = "GPIO";
interrupts = <4 1 0>;
interrupt-parent = <&dw_intc>;
gpio-controller;
#gpio-cells = <2>;
};
uart0: uart@80800 {
compatible = "ns16550";

19
soc/xtensa/intel_s1000/dts_fixup.h
View file

@ -58,4 +58,23 @@
#define DT_SPI_DW_IRQ_FLAGS DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0_SENSE
#define DT_SPI_0_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0_PRIORITY
#define DT_GPIO_DW_0_BASE_ADDR \
DT_SNPS_DESIGNWARE_GPIO_80C00_BASE_ADDRESS
#define DT_GPIO_DW_0_BITS \
DT_SNPS_DESIGNWARE_GPIO_80C00_BITS
#define DT_GPIO_INTC_IRQ \
(DT_SNPS_DESIGNWARE_GPIO_80C00_IRQ_0 << INTR_CNTL_IRQ_NUM_SHIFT)
#define DT_GPIO_CAVS_IRQ \
(DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0 << CAVS_IRQ_NUM_SHIFT)
#define DT_GPIO_XTENSA_IRQ \
(DT_INTEL_CAVS_INTC_78800_IRQ_0 << XTENSA_IRQ_NUM_SHIFT)
#define DT_GPIO_DW_0_IRQ \
(DT_GPIO_INTC_IRQ | DT_GPIO_CAVS_IRQ | DT_GPIO_XTENSA_IRQ)
#define CONFIG_GPIO_DW_0_IRQ_PRI \
DT_SNPS_DESIGNWARE_GPIO_80C00_IRQ_0_PRIORITY
#define DT_GPIO_DW_0_IRQ_FLAGS 0
#define CONFIG_GPIO_DW_0_NAME \
DT_SNPS_DESIGNWARE_GPIO_80C00_LABEL
/* End of SoC Level DTS fixup file */

5
soc/xtensa/intel_s1000/soc.h
View file

@ -36,12 +36,7 @@
#define DW_ICTL_NUM_IRQS 9
/* GPIO */
#define DT_GPIO_DW_0_BASE_ADDR 0x00080C00
#define DT_GPIO_DW_0_BITS 32
#define GPIO_DW_PORT_0_INT_MASK 0
#define DT_GPIO_DW_0_IRQ_FLAGS 0
#define DT_GPIO_DW_0_IRQ 0x00040706
#define GPIO_DW_0_IRQ_ICTL_OFFSET INTR_CNTL_IRQ_NUM(DT_GPIO_DW_0_IRQ)
/* low power DMACs */
#define LP_GP_DMA_SIZE 0x00001000