drivers: timer: split Kconfig
Split Kconfig into individual files for each driver. This improves overall readability of the Kconfig options. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This commit is contained in:
Gerard Marull-Paretas
Anas Nashif
parent
b1ced75386
commit
24a169e329
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@ -7,379 +7,6 @@
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menu "Timer Drivers"
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config TIMER_HAS_64BIT_CYCLE_COUNTER
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bool
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help
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When this option is true, the k_cycle_get_64() call is
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available to provide values from a 64-bit cycle counter.
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menuconfig APIC_TIMER
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bool "New local APIC timer"
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depends on X86
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depends on LOAPIC
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select TICKLESS_CAPABLE
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help
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Use the x86 local APIC in one-shot mode as the system time
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source. NOTE: this probably isn't what you want except on
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older or idiosyncratic hardware (or environments like qemu
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without complete APIC emulation). Modern hardware will work
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better with CONFIG_APIC_TSC_DEADLINE_TIMER.
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if APIC_TIMER
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config APIC_TIMER_IRQ
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int "Local APIC timer IRQ"
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default 24
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help
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This option specifies the IRQ used by the local APIC timer.
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Note: this MUST be set to the index immediately after the
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last IO-APIC IRQ (the timer is the first entry in the APIC
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local vector table). This footgun is not intended to be
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user-configurable and almost certainly should be managed via
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a different mechanism.
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config APIC_TIMER_TSC
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bool "Use invariant TSC for sys_clock_cycle_get_32()"
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select TIMER_HAS_64BIT_CYCLE_COUNTER
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help
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If your CPU supports invariant TSC, and you know the ratio of the
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TSC frequency to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC (the local APIC
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timer frequency), then enable this for a much faster and more
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accurate sys_clock_cycle_get_32().
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if APIC_TIMER_TSC
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config APIC_TIMER_TSC_N
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int "TSC to local APIC timer frequency multiplier (N)"
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default 1
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config APIC_TIMER_TSC_M
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int "TSC to local APIC timer frequency divisor (M)"
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default 1
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endif # APIC_TIMER_TSC
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endif # APIC_TIMER
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config APIC_TSC_DEADLINE_TIMER
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bool "Even newer APIC timer using TSC deadline mode"
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depends on X86
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select LOAPIC
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select TICKLESS_CAPABLE
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help
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Extremely simple timer driver based the local APIC TSC
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deadline capability. The use of a free-running 64 bit
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counter with comparator eliminates almost all edge cases
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from the handling, and the near-instruction-cycle resolution
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permits effectively unlimited precision where needed (the
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limit becomes the CPU time taken to execute the timing
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logic). SMP-safe and very fast, this should be the obvious
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choice for any x86 device with invariant TSC and TSC
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deadline capability.
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config APIC_TIMER_IRQ_PRIORITY
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int "Local APIC timer interrupt priority"
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depends on APIC_TIMER || APIC_TSC_DEADLINE_TIMER
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default 4
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help
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This option specifies the interrupt priority used by the
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local APIC timer.
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config HPET_TIMER
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bool "HPET timer"
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select IOAPIC if X86
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select LOAPIC if X86
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imply TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
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select TICKLESS_CAPABLE
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select TIMER_HAS_64BIT_CYCLE_COUNTER
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help
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This option selects High Precision Event Timer (HPET) as a
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system timer.
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menuconfig ARCV2_TIMER
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bool "ARC Timer"
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default y
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depends on ARC
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select TICKLESS_CAPABLE
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help
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This module implements a kernel device driver for the ARCv2 processor timer 0
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and provides the standard "system clock driver" interfaces.
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config ARCV2_TIMER_IRQ_PRIORITY
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int "ARC timer interrupt priority"
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default 0
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depends on ARCV2_TIMER
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help
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This option specifies the IRQ priority used by the ARC timer. Lower
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values have higher priority.
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config ARM_ARCH_TIMER
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bool "ARM architected timer"
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depends on GIC
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select ARCH_HAS_CUSTOM_BUSY_WAIT
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select TICKLESS_CAPABLE
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select TIMER_HAS_64BIT_CYCLE_COUNTER
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help
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This module implements a kernel device driver for the ARM architected
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timer which provides per-cpu timers attached to a GIC to deliver its
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per-processor interrupts via PPIs.
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DT_COMPAT_ARM_V6M_SYSTICK := arm,armv6m-systick
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DT_COMPAT_ARM_V7M_SYSTICK := arm,armv7m-systick
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DT_COMPAT_ARM_V8M_SYSTICK := arm,armv8m-systick
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DT_COMPAT_ARM_V8_1M_SYSTICK := arm,armv8.1m-systick
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config ARM_ARCH_TIMER_ERRATUM_740657
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bool "ARM architected timer is affected by ARM erratum 740657"
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depends on ARM_ARCH_TIMER
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help
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This option indicates that the ARM architected timer as implemented
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in the target hardware is affected by the ARM erratum 740657 (comp.
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ARM Cortex-A9 processors Software Developers Errata Notice, ARM
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document ID032315) which leads to an additional, spurious interrupt
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indication upon every actual timer interrupt. This option activates
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the workaround for the erratum within the timer driver.
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config CORTEX_M_SYSTICK
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bool "Cortex-M SYSTICK timer"
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depends on CPU_CORTEX_M_HAS_SYSTICK
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default $(dt_compat_enabled,$(DT_COMPAT_ARM_V6M_SYSTICK)) || \
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$(dt_compat_enabled,$(DT_COMPAT_ARM_V7M_SYSTICK)) || \
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$(dt_compat_enabled,$(DT_COMPAT_ARM_V8M_SYSTICK)) || \
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$(dt_compat_enabled,$(DT_COMPAT_ARM_V8_1M_SYSTICK))
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select TICKLESS_CAPABLE
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help
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This module implements a kernel device driver for the Cortex-M processor
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SYSTICK timer and provides the standard "system clock driver" interfaces.
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config ALTERA_AVALON_TIMER
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bool "Altera Avalon Interval Timer"
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default y
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depends on NIOS2
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help
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This module implements a kernel device driver for the Altera Avalon
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Interval Timer as described in the Embedded IP documentation, for use
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with Nios II and possibly other Altera soft CPUs. It provides the
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standard "system clock driver" interfaces.
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config ITE_IT8XXX2_TIMER
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bool "ITE it8xxx2 timer driver"
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depends on SOC_IT8XXX2
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select TICKLESS_CAPABLE
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help
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This module implements a kernel device driver for the ITE it8xxx2
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HW timer model
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config NRF_RTC_TIMER
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bool "nRF Real Time Counter (NRF_RTC1) Timer"
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depends on CLOCK_CONTROL
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depends on SOC_COMPATIBLE_NRF
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select TICKLESS_CAPABLE
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select NRF_HW_RTC1_RESERVED
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help
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This module implements a kernel device driver for the nRF Real Time
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Counter NRF_RTC1 and provides the standard "system clock driver"
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interfaces.
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if NRF_RTC_TIMER
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config NRF_RTC_TIMER_USER_CHAN_COUNT
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int "Additional channels that can be used"
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default 0
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help
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Use nrf_rtc_timer.h API. Driver is not managing allocation of channels.
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choice
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prompt "Clock startup policy"
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default SYSTEM_CLOCK_WAIT_FOR_STABILITY
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config SYSTEM_CLOCK_NO_WAIT
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bool "No wait"
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help
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System clock source is initiated but does not wait for clock readiness.
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When this option is picked, system clock may not be ready when code relying
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on kernel API is executed. Requested timeouts will be prolonged by the
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remaining startup time.
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config SYSTEM_CLOCK_WAIT_FOR_AVAILABILITY
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bool "Wait for availability"
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help
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System clock source initialization waits until clock is available. In some
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systems, clock initially runs from less accurate source which has faster
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startup time and then seamlessly switches to the target clock source when
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it is ready. When this option is picked, system clock is available after
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system clock driver initialization but it may be less accurate. Option is
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equivalent to waiting for stability if clock source does not have
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intermediate state.
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config SYSTEM_CLOCK_WAIT_FOR_STABILITY
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bool "Wait for stability"
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help
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System clock source initialization waits until clock is stable. When this
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option is picked, system clock is available and stable after system clock
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driver initialization.
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endchoice
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endif # NRF_RTC_TIMER
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source "drivers/timer/Kconfig.stm32_lptim"
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config RISCV_MACHINE_TIMER
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bool "RISCV Machine Timer"
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depends on SOC_FAMILY_RISCV_PRIVILEGE
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select TICKLESS_CAPABLE
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select TIMER_HAS_64BIT_CYCLE_COUNTER
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help
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This module implements a kernel device driver for the generic RISCV machine
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timer driver. It provides the standard "system clock driver" interfaces.
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config RV32M1_LPTMR_TIMER
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bool "RV32M1 LPTMR system timer driver"
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default y
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depends on SOC_OPENISA_RV32M1_RISCV32
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depends on RV32M1_INTMUX
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help
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This module implements a kernel device driver for using the LPTMR
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peripheral as the system clock. It provides the standard "system clock
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driver" interfaces.
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config LITEX_TIMER
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bool "LiteX Timer"
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default y
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depends on SOC_RISCV32_LITEX_VEXRISCV
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select TIMER_HAS_64BIT_CYCLE_COUNTER
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help
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This module implements a kernel device driver for LiteX Timer.
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config NATIVE_POSIX_TIMER
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bool "(POSIX) native_posix timer driver"
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default y
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depends on BOARD_NATIVE_POSIX
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select TICKLESS_CAPABLE
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select TIMER_HAS_64BIT_CYCLE_COUNTER
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help
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This module implements a kernel device driver for the native_posix HW timer
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model
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config XTENSA_TIMER
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bool "Xtensa timer support"
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depends on XTENSA
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default y
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select TICKLESS_CAPABLE
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help
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Enables a system timer driver for Xtensa based on the CCOUNT
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and CCOMPARE special registers.
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config ESP32C3_SYS_TIMER
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bool "ESP32C3 sys-timer support"
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depends on SOC_ESP32C3
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default y
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select TICKLESS_CAPABLE
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select TIMER_HAS_64BIT_CYCLE_COUNTER
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help
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This option enables the system timer driver for the Espressif ESP32C3
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and provides the standard "system clock driver" interface.
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config XTENSA_TIMER_ID
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int "System timer CCOMPAREn register index"
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default 1
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depends on XTENSA_TIMER
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help
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Index of the CCOMPARE register (and associated interrupt)
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used for the system timer. Xtensa CPUs have hard-configured
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interrupt priorities associated with each timer, and some of
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them can be unmaskable (and thus not usable by OS code that
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need synchronization, like the timer subsystem!). Choose
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carefully. Generally you want the timer with the highest
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priority maskable interrupt.
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config SAM0_RTC_TIMER
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bool "Atmel SAM0 series RTC timer"
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depends on SOC_FAMILY_SAM0
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select TICKLESS_CAPABLE
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help
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This module implements a kernel device driver for the Atmel SAM0
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series Real Time Counter and provides the standard "system clock
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driver" interfaces.
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config MCHP_XEC_RTOS_TIMER
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bool "Microchip XEC series RTOS timer"
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depends on SOC_FAMILY_MEC
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select TICKLESS_CAPABLE
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help
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This module implements a kernel device driver for the Microchip
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XEC series RTOS timer and provides the standard "system clock
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driver" interfaces.
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config CC13X2_CC26X2_RTC_TIMER
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bool "TI SimpleLink CC13x2/CC26x2 RTC timer"
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depends on SOC_SERIES_CC13X2_CC26X2
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select TICKLESS_CAPABLE
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select TIMER_HAS_64BIT_CYCLE_COUNTER
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help
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This module implements a kernel device driver for the TI SimpleLink
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CC13X2_CC26X2 series Real Time Counter and provides the standard
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"system clock driver" interfaces.
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config RCAR_CMT_TIMER
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bool "Renesas RCar cmt timer"
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default y
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depends on SOC_SERIES_RCAR_GEN3
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help
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This module implements a kernel device driver for the Renesas RCAR
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platform provides the standard "system clock driver" interfaces.
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If unchecked, no timer will be used.
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config XLNX_PSTTC_TIMER
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bool "Xilinx PS ttc timer support"
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default y
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depends on SOC_XILINX_ZYNQMP
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select TICKLESS_CAPABLE
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help
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This module implements a kernel device driver for the Xilinx ZynqMP
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platform provides the standard "system clock driver" interfaces.
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If unchecked, no timer will be used.
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config XLNX_PSTTC_TIMER_INDEX
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int "Xilinx PS ttc timer index"
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range 0 3
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default 0
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depends on XLNX_PSTTC_TIMER
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help
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This is the index of TTC timer picked to provide system clock.
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config CAVS_TIMER
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bool "CAVS DSP Wall Clock Timer on Intel SoC"
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depends on CAVS_ICTL
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select TICKLESS_CAPABLE
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select TIMER_HAS_64BIT_CYCLE_COUNTER
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help
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The DSP wall clock timer is a timer driven directly by
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external oscillator and is external to the CPU core(s).
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It is not as fast as the internal core clock, but provides
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a common and synchronized counter for all CPU cores (which
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is useful for SMP).
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config LEON_GPTIMER
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bool "LEON timer"
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depends on SOC_SPARC_LEON
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select DYNAMIC_INTERRUPTS
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help
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This module implements a kernel device driver for the GRLIB
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GPTIMER which is common in LEON systems.
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config NPCX_ITIM_TIMER
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bool "Nuvoton NPCX series internal 64/32-bit timers"
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default y
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depends on SOC_FAMILY_NPCX
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select TICKLESS_CAPABLE
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select TIMER_HAS_64BIT_CYCLE_COUNTER
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help
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This module implements a kernel device driver for the Nuvoton NPCX
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series internal 64/32-bit timers and provides the standard "system
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clock driver" interfaces.
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config SYSTEM_CLOCK_DISABLE
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bool "API to disable system clock"
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help
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@ -387,6 +14,12 @@ config SYSTEM_CLOCK_DISABLE
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needed by some subsystems (which will automatically select it), but is
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rarely needed by applications.
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config TIMER_HAS_64BIT_CYCLE_COUNTER
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bool
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help
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When this option is true, the k_cycle_get_64() call is
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available to provide values from a 64-bit cycle counter.
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config TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
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bool "Timer queries its hardware to find its frequency at runtime"
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help
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@ -422,24 +55,30 @@ config TICKLESS_CAPABLE
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sys_clock_announce() (really, not to produce an interrupt at
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all) until the specified expiration.
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DT_COMPAT_NXP_OS_TIMER := nxp,os-timer
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config MCUX_OS_TIMER
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bool "MCUX OS Event timer"
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depends on HAS_MCUX_OS_TIMER
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default $(dt_compat_enabled,$(DT_COMPAT_NXP_OS_TIMER))
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select TICKLESS_CAPABLE
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select TIMER_HAS_64BIT_CYCLE_COUNTER
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help
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This module implements a kernel device driver for the NXP OS
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event timer and provides the standard "system clock driver" interfaces.
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config MCUX_LPTMR_TIMER
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bool "MCUX LPTMR timer"
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depends on HAS_MCUX_LPTMR && !COUNTER_MCUX_LPTMR
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help
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This module implements a kernel device driver for the NXP MCUX Low
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Power Timer (LPTMR) and provides the standard "system clock driver"
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interfaces.
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source "drivers/timer/Kconfig.altera_avalon"
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source "drivers/timer/Kconfig.apic"
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source "drivers/timer/Kconfig.arcv2"
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source "drivers/timer/Kconfig.arm_arch"
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source "drivers/timer/Kconfig.cavs"
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source "drivers/timer/Kconfig.cc13x2_cc26x2_rtc"
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source "drivers/timer/Kconfig.cortex_m_systick"
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source "drivers/timer/Kconfig.esp32c3_sys"
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source "drivers/timer/Kconfig.hpet"
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source "drivers/timer/Kconfig.ite_it8xxx2"
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source "drivers/timer/Kconfig.leon_gptimer"
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source "drivers/timer/Kconfig.litex"
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source "drivers/timer/Kconfig.mchp_xec_rtos"
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source "drivers/timer/Kconfig.mcux_lptmr"
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source "drivers/timer/Kconfig.mcux_os"
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source "drivers/timer/Kconfig.native_posix"
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source "drivers/timer/Kconfig.npcx_itim"
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source "drivers/timer/Kconfig.nrf_rtc"
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source "drivers/timer/Kconfig.rcar_cmt"
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source "drivers/timer/Kconfig.riscv_machine"
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source "drivers/timer/Kconfig.rv32m1_lptmr"
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source "drivers/timer/Kconfig.sam0_rtc"
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source "drivers/timer/Kconfig.stm32_lptim"
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source "drivers/timer/Kconfig.xlnx_psttc"
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source "drivers/timer/Kconfig.xtensa"
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endmenu
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14
drivers/timer/Kconfig.altera_avalon
Normal file
14
drivers/timer/Kconfig.altera_avalon
Normal file
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@ -0,0 +1,14 @@
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# Copyright (c) 2014-2015 Wind River Systems, Inc.
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# Copyright (c) 2016 Cadence Design Systems, Inc.
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# Copyright (c) 2019 Intel Corp.
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# SPDX-License-Identifier: Apache-2.0
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config ALTERA_AVALON_TIMER
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bool "Altera Avalon Interval Timer"
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default y
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depends on NIOS2
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||||
help
|
||||
This module implements a kernel device driver for the Altera Avalon
|
||||
Interval Timer as described in the Embedded IP documentation, for use
|
||||
with Nios II and possibly other Altera soft CPUs. It provides the
|
||||
standard "system clock driver" interfaces.
|
||||
76
drivers/timer/Kconfig.apic
Normal file
76
drivers/timer/Kconfig.apic
Normal file
|
|
@ -0,0 +1,76 @@
|
|||
# Copyright (c) 2014-2015 Wind River Systems, Inc.
|
||||
# Copyright (c) 2016 Cadence Design Systems, Inc.
|
||||
# Copyright (c) 2019 Intel Corp.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
menuconfig APIC_TIMER
|
||||
bool "New local APIC timer"
|
||||
depends on X86
|
||||
depends on LOAPIC
|
||||
select TICKLESS_CAPABLE
|
||||
help
|
||||
Use the x86 local APIC in one-shot mode as the system time
|
||||
source. NOTE: this probably isn't what you want except on
|
||||
older or idiosyncratic hardware (or environments like qemu
|
||||
without complete APIC emulation). Modern hardware will work
|
||||
better with CONFIG_APIC_TSC_DEADLINE_TIMER.
|
||||
|
||||
if APIC_TIMER
|
||||
|
||||
config APIC_TIMER_IRQ
|
||||
int "Local APIC timer IRQ"
|
||||
default 24
|
||||
help
|
||||
This option specifies the IRQ used by the local APIC timer.
|
||||
Note: this MUST be set to the index immediately after the
|
||||
last IO-APIC IRQ (the timer is the first entry in the APIC
|
||||
local vector table). This footgun is not intended to be
|
||||
user-configurable and almost certainly should be managed via
|
||||
a different mechanism.
|
||||
|
||||
config APIC_TIMER_TSC
|
||||
bool "Use invariant TSC for sys_clock_cycle_get_32()"
|
||||
select TIMER_HAS_64BIT_CYCLE_COUNTER
|
||||
help
|
||||
If your CPU supports invariant TSC, and you know the ratio of the
|
||||
TSC frequency to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC (the local APIC
|
||||
timer frequency), then enable this for a much faster and more
|
||||
accurate sys_clock_cycle_get_32().
|
||||
|
||||
if APIC_TIMER_TSC
|
||||
|
||||
config APIC_TIMER_TSC_N
|
||||
int "TSC to local APIC timer frequency multiplier (N)"
|
||||
default 1
|
||||
|
||||
config APIC_TIMER_TSC_M
|
||||
int "TSC to local APIC timer frequency divisor (M)"
|
||||
default 1
|
||||
|
||||
endif # APIC_TIMER_TSC
|
||||
|
||||
endif # APIC_TIMER
|
||||
|
||||
config APIC_TSC_DEADLINE_TIMER
|
||||
bool "Even newer APIC timer using TSC deadline mode"
|
||||
depends on X86
|
||||
select LOAPIC
|
||||
select TICKLESS_CAPABLE
|
||||
help
|
||||
Extremely simple timer driver based the local APIC TSC
|
||||
deadline capability. The use of a free-running 64 bit
|
||||
counter with comparator eliminates almost all edge cases
|
||||
from the handling, and the near-instruction-cycle resolution
|
||||
permits effectively unlimited precision where needed (the
|
||||
limit becomes the CPU time taken to execute the timing
|
||||
logic). SMP-safe and very fast, this should be the obvious
|
||||
choice for any x86 device with invariant TSC and TSC
|
||||
deadline capability.
|
||||
|
||||
config APIC_TIMER_IRQ_PRIORITY
|
||||
int "Local APIC timer interrupt priority"
|
||||
depends on APIC_TIMER || APIC_TSC_DEADLINE_TIMER
|
||||
default 4
|
||||
help
|
||||
This option specifies the interrupt priority used by the
|
||||
local APIC timer.
|
||||
21
drivers/timer/Kconfig.arcv2
Normal file
21
drivers/timer/Kconfig.arcv2
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
# Copyright (c) 2014-2015 Wind River Systems, Inc.
|
||||
# Copyright (c) 2016 Cadence Design Systems, Inc.
|
||||
# Copyright (c) 2019 Intel Corp.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
menuconfig ARCV2_TIMER
|
||||
bool "ARC Timer"
|
||||
default y
|
||||
depends on ARC
|
||||
select TICKLESS_CAPABLE
|
||||
help
|
||||
This module implements a kernel device driver for the ARCv2 processor timer 0
|
||||
and provides the standard "system clock driver" interfaces.
|
||||
|
||||
config ARCV2_TIMER_IRQ_PRIORITY
|
||||
int "ARC timer interrupt priority"
|
||||
default 0
|
||||
depends on ARCV2_TIMER
|
||||
help
|
||||
This option specifies the IRQ priority used by the ARC timer. Lower
|
||||
values have higher priority.
|
||||
26
drivers/timer/Kconfig.arm_arch
Normal file
26
drivers/timer/Kconfig.arm_arch
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
# Copyright (c) 2014-2015 Wind River Systems, Inc.
|
||||
# Copyright (c) 2016 Cadence Design Systems, Inc.
|
||||
# Copyright (c) 2019 Intel Corp.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config ARM_ARCH_TIMER
|
||||
bool "ARM architected timer"
|
||||
depends on GIC
|
||||
select ARCH_HAS_CUSTOM_BUSY_WAIT
|
||||
select TICKLESS_CAPABLE
|
||||
select TIMER_HAS_64BIT_CYCLE_COUNTER
|
||||
help
|
||||
This module implements a kernel device driver for the ARM architected
|
||||
timer which provides per-cpu timers attached to a GIC to deliver its
|
||||
per-processor interrupts via PPIs.
|
||||
|
||||
config ARM_ARCH_TIMER_ERRATUM_740657
|
||||
bool "ARM architected timer is affected by ARM erratum 740657"
|
||||
depends on ARM_ARCH_TIMER
|
||||
help
|
||||
This option indicates that the ARM architected timer as implemented
|
||||
in the target hardware is affected by the ARM erratum 740657 (comp.
|
||||
ARM Cortex-A9 processors Software Developers Errata Notice, ARM
|
||||
document ID032315) which leads to an additional, spurious interrupt
|
||||
indication upon every actual timer interrupt. This option activates
|
||||
the workaround for the erratum within the timer driver.
|
||||
16
drivers/timer/Kconfig.cavs
Normal file
16
drivers/timer/Kconfig.cavs
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
# Copyright (c) 2014-2015 Wind River Systems, Inc.
|
||||
# Copyright (c) 2016 Cadence Design Systems, Inc.
|
||||
# Copyright (c) 2019 Intel Corp.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config CAVS_TIMER
|
||||
bool "CAVS DSP Wall Clock Timer on Intel SoC"
|
||||
depends on CAVS_ICTL
|
||||
select TICKLESS_CAPABLE
|
||||
select TIMER_HAS_64BIT_CYCLE_COUNTER
|
||||
help
|
||||
The DSP wall clock timer is a timer driven directly by
|
||||
external oscillator and is external to the CPU core(s).
|
||||
It is not as fast as the internal core clock, but provides
|
||||
a common and synchronized counter for all CPU cores (which
|
||||
is useful for SMP).
|
||||
14
drivers/timer/Kconfig.cc13x2_cc26x2_rtc
Normal file
14
drivers/timer/Kconfig.cc13x2_cc26x2_rtc
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
# Copyright (c) 2014-2015 Wind River Systems, Inc.
|
||||
# Copyright (c) 2016 Cadence Design Systems, Inc.
|
||||
# Copyright (c) 2019 Intel Corp.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config CC13X2_CC26X2_RTC_TIMER
|
||||
bool "TI SimpleLink CC13x2/CC26x2 RTC timer"
|
||||
depends on SOC_SERIES_CC13X2_CC26X2
|
||||
select TICKLESS_CAPABLE
|
||||
select TIMER_HAS_64BIT_CYCLE_COUNTER
|
||||
help
|
||||
This module implements a kernel device driver for the TI SimpleLink
|
||||
CC13X2_CC26X2 series Real Time Counter and provides the standard
|
||||
"system clock driver" interfaces.
|
||||
21
drivers/timer/Kconfig.cortex_m_systick
Normal file
21
drivers/timer/Kconfig.cortex_m_systick
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
# Copyright (c) 2014-2015 Wind River Systems, Inc.
|
||||
# Copyright (c) 2016 Cadence Design Systems, Inc.
|
||||
# Copyright (c) 2019 Intel Corp.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
DT_COMPAT_ARM_V6M_SYSTICK := arm,armv6m-systick
|
||||
DT_COMPAT_ARM_V7M_SYSTICK := arm,armv7m-systick
|
||||
DT_COMPAT_ARM_V8M_SYSTICK := arm,armv8m-systick
|
||||
DT_COMPAT_ARM_V8_1M_SYSTICK := arm,armv8.1m-systick
|
||||
|
||||
config CORTEX_M_SYSTICK
|
||||
bool "Cortex-M SYSTICK timer"
|
||||
depends on CPU_CORTEX_M_HAS_SYSTICK
|
||||
default $(dt_compat_enabled,$(DT_COMPAT_ARM_V6M_SYSTICK)) || \
|
||||
$(dt_compat_enabled,$(DT_COMPAT_ARM_V7M_SYSTICK)) || \
|
||||
$(dt_compat_enabled,$(DT_COMPAT_ARM_V8M_SYSTICK)) || \
|
||||
$(dt_compat_enabled,$(DT_COMPAT_ARM_V8_1M_SYSTICK))
|
||||
select TICKLESS_CAPABLE
|
||||
help
|
||||
This module implements a kernel device driver for the Cortex-M processor
|
||||
SYSTICK timer and provides the standard "system clock driver" interfaces.
|
||||
14
drivers/timer/Kconfig.esp32c3_sys
Normal file
14
drivers/timer/Kconfig.esp32c3_sys
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
# Copyright (c) 2014-2015 Wind River Systems, Inc.
|
||||
# Copyright (c) 2016 Cadence Design Systems, Inc.
|
||||
# Copyright (c) 2019 Intel Corp.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config ESP32C3_SYS_TIMER
|
||||
bool "ESP32C3 sys-timer support"
|
||||
depends on SOC_ESP32C3
|
||||
default y
|
||||
select TICKLESS_CAPABLE
|
||||
select TIMER_HAS_64BIT_CYCLE_COUNTER
|
||||
help
|
||||
This option enables the system timer driver for the Espressif ESP32C3
|
||||
and provides the standard "system clock driver" interface.
|
||||
15
drivers/timer/Kconfig.hpet
Normal file
15
drivers/timer/Kconfig.hpet
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
# Copyright (c) 2014-2015 Wind River Systems, Inc.
|
||||
# Copyright (c) 2016 Cadence Design Systems, Inc.
|
||||
# Copyright (c) 2019 Intel Corp.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config HPET_TIMER
|
||||
bool "HPET timer"
|
||||
select IOAPIC if X86
|
||||
select LOAPIC if X86
|
||||
imply TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
|
||||
select TICKLESS_CAPABLE
|
||||
select TIMER_HAS_64BIT_CYCLE_COUNTER
|
||||
help
|
||||
This option selects High Precision Event Timer (HPET) as a
|
||||
system timer.
|
||||
12
drivers/timer/Kconfig.ite_it8xxx2
Normal file
12
drivers/timer/Kconfig.ite_it8xxx2
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
# Copyright (c) 2014-2015 Wind River Systems, Inc.
|
||||
# Copyright (c) 2016 Cadence Design Systems, Inc.
|
||||
# Copyright (c) 2019 Intel Corp.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config ITE_IT8XXX2_TIMER
|
||||
bool "ITE it8xxx2 timer driver"
|
||||
depends on SOC_IT8XXX2
|
||||
select TICKLESS_CAPABLE
|
||||
help
|
||||
This module implements a kernel device driver for the ITE it8xxx2
|
||||
HW timer model
|
||||
12
drivers/timer/Kconfig.leon_gptimer
Normal file
12
drivers/timer/Kconfig.leon_gptimer
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
# Copyright (c) 2014-2015 Wind River Systems, Inc.
|
||||
# Copyright (c) 2016 Cadence Design Systems, Inc.
|
||||
# Copyright (c) 2019 Intel Corp.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config LEON_GPTIMER
|
||||
bool "LEON timer"
|
||||
depends on SOC_SPARC_LEON
|
||||
select DYNAMIC_INTERRUPTS
|
||||
help
|
||||
This module implements a kernel device driver for the GRLIB
|
||||
GPTIMER which is common in LEON systems.
|
||||
12
drivers/timer/Kconfig.litex
Normal file
12
drivers/timer/Kconfig.litex
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
# Copyright (c) 2014-2015 Wind River Systems, Inc.
|
||||
# Copyright (c) 2016 Cadence Design Systems, Inc.
|
||||
# Copyright (c) 2019 Intel Corp.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config LITEX_TIMER
|
||||
bool "LiteX Timer"
|
||||
default y
|
||||
depends on SOC_RISCV32_LITEX_VEXRISCV
|
||||
select TIMER_HAS_64BIT_CYCLE_COUNTER
|
||||
help
|
||||
This module implements a kernel device driver for LiteX Timer.
|
||||
13
drivers/timer/Kconfig.mchp_xec_rtos
Normal file
13
drivers/timer/Kconfig.mchp_xec_rtos
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
# Copyright (c) 2014-2015 Wind River Systems, Inc.
|
||||
# Copyright (c) 2016 Cadence Design Systems, Inc.
|
||||
# Copyright (c) 2019 Intel Corp.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config MCHP_XEC_RTOS_TIMER
|
||||
bool "Microchip XEC series RTOS timer"
|
||||
depends on SOC_FAMILY_MEC
|
||||
select TICKLESS_CAPABLE
|
||||
help
|
||||
This module implements a kernel device driver for the Microchip
|
||||
XEC series RTOS timer and provides the standard "system clock
|
||||
driver" interfaces.
|
||||
12
drivers/timer/Kconfig.mcux_lptmr
Normal file
12
drivers/timer/Kconfig.mcux_lptmr
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
# Copyright (c) 2014-2015 Wind River Systems, Inc.
|
||||
# Copyright (c) 2016 Cadence Design Systems, Inc.
|
||||
# Copyright (c) 2019 Intel Corp.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config MCUX_LPTMR_TIMER
|
||||
bool "MCUX LPTMR timer"
|
||||
depends on HAS_MCUX_LPTMR && !COUNTER_MCUX_LPTMR
|
||||
help
|
||||
This module implements a kernel device driver for the NXP MCUX Low
|
||||
Power Timer (LPTMR) and provides the standard "system clock driver"
|
||||
interfaces.
|
||||
15
drivers/timer/Kconfig.mcux_os
Normal file
15
drivers/timer/Kconfig.mcux_os
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
# Copyright (c) 2014-2015 Wind River Systems, Inc.
|
||||
# Copyright (c) 2016 Cadence Design Systems, Inc.
|
||||
# Copyright (c) 2019 Intel Corp.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
DT_COMPAT_NXP_OS_TIMER := nxp,os-timer
|
||||
|
||||
config MCUX_OS_TIMER
|
||||
bool "MCUX OS Event timer"
|
||||
depends on HAS_MCUX_OS_TIMER
|
||||
default $(dt_compat_enabled,$(DT_COMPAT_NXP_OS_TIMER))
|
||||
select TICKLESS_CAPABLE
|
||||
help
|
||||
This module implements a kernel device driver for the NXP OS
|
||||
event timer and provides the standard "system clock driver" interfaces.
|
||||
14
drivers/timer/Kconfig.native_posix
Normal file
14
drivers/timer/Kconfig.native_posix
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
# Copyright (c) 2014-2015 Wind River Systems, Inc.
|
||||
# Copyright (c) 2016 Cadence Design Systems, Inc.
|
||||
# Copyright (c) 2019 Intel Corp.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config NATIVE_POSIX_TIMER
|
||||
bool "(POSIX) native_posix timer driver"
|
||||
default y
|
||||
depends on BOARD_NATIVE_POSIX
|
||||
select TICKLESS_CAPABLE
|
||||
select TIMER_HAS_64BIT_CYCLE_COUNTER
|
||||
help
|
||||
This module implements a kernel device driver for the native_posix HW timer
|
||||
model
|
||||
15
drivers/timer/Kconfig.npcx_itim
Normal file
15
drivers/timer/Kconfig.npcx_itim
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
# Copyright (c) 2014-2015 Wind River Systems, Inc.
|
||||
# Copyright (c) 2016 Cadence Design Systems, Inc.
|
||||
# Copyright (c) 2019 Intel Corp.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config NPCX_ITIM_TIMER
|
||||
bool "Nuvoton NPCX series internal 64/32-bit timers"
|
||||
default y
|
||||
depends on SOC_FAMILY_NPCX
|
||||
select TICKLESS_CAPABLE
|
||||
select TIMER_HAS_64BIT_CYCLE_COUNTER
|
||||
help
|
||||
This module implements a kernel device driver for the Nuvoton NPCX
|
||||
series internal 64/32-bit timers and provides the standard "system
|
||||
clock driver" interfaces.
|
||||
57
drivers/timer/Kconfig.nrf_rtc
Normal file
57
drivers/timer/Kconfig.nrf_rtc
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
# Copyright (c) 2014-2015 Wind River Systems, Inc.
|
||||
# Copyright (c) 2016 Cadence Design Systems, Inc.
|
||||
# Copyright (c) 2019 Intel Corp.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config NRF_RTC_TIMER
|
||||
bool "nRF Real Time Counter (NRF_RTC1) Timer"
|
||||
depends on CLOCK_CONTROL
|
||||
depends on SOC_COMPATIBLE_NRF
|
||||
select TICKLESS_CAPABLE
|
||||
select NRF_HW_RTC1_RESERVED
|
||||
help
|
||||
This module implements a kernel device driver for the nRF Real Time
|
||||
Counter NRF_RTC1 and provides the standard "system clock driver"
|
||||
interfaces.
|
||||
|
||||
if NRF_RTC_TIMER
|
||||
|
||||
config NRF_RTC_TIMER_USER_CHAN_COUNT
|
||||
int "Additional channels that can be used"
|
||||
default 0
|
||||
help
|
||||
Use nrf_rtc_timer.h API. Driver is not managing allocation of channels.
|
||||
|
||||
choice
|
||||
prompt "Clock startup policy"
|
||||
default SYSTEM_CLOCK_WAIT_FOR_STABILITY
|
||||
|
||||
config SYSTEM_CLOCK_NO_WAIT
|
||||
bool "No wait"
|
||||
help
|
||||
System clock source is initiated but does not wait for clock readiness.
|
||||
When this option is picked, system clock may not be ready when code relying
|
||||
on kernel API is executed. Requested timeouts will be prolonged by the
|
||||
remaining startup time.
|
||||
|
||||
config SYSTEM_CLOCK_WAIT_FOR_AVAILABILITY
|
||||
bool "Wait for availability"
|
||||
help
|
||||
System clock source initialization waits until clock is available. In some
|
||||
systems, clock initially runs from less accurate source which has faster
|
||||
startup time and then seamlessly switches to the target clock source when
|
||||
it is ready. When this option is picked, system clock is available after
|
||||
system clock driver initialization but it may be less accurate. Option is
|
||||
equivalent to waiting for stability if clock source does not have
|
||||
intermediate state.
|
||||
|
||||
config SYSTEM_CLOCK_WAIT_FOR_STABILITY
|
||||
bool "Wait for stability"
|
||||
help
|
||||
System clock source initialization waits until clock is stable. When this
|
||||
option is picked, system clock is available and stable after system clock
|
||||
driver initialization.
|
||||
|
||||
endchoice
|
||||
|
||||
endif # NRF_RTC_TIMER
|
||||
13
drivers/timer/Kconfig.rcar_cmt
Normal file
13
drivers/timer/Kconfig.rcar_cmt
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
# Copyright (c) 2014-2015 Wind River Systems, Inc.
|
||||
# Copyright (c) 2016 Cadence Design Systems, Inc.
|
||||
# Copyright (c) 2019 Intel Corp.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config RCAR_CMT_TIMER
|
||||
bool "Renesas RCar cmt timer"
|
||||
default y
|
||||
depends on SOC_SERIES_RCAR_GEN3
|
||||
help
|
||||
This module implements a kernel device driver for the Renesas RCAR
|
||||
platform provides the standard "system clock driver" interfaces.
|
||||
If unchecked, no timer will be used.
|
||||
13
drivers/timer/Kconfig.riscv_machine
Normal file
13
drivers/timer/Kconfig.riscv_machine
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
# Copyright (c) 2014-2015 Wind River Systems, Inc.
|
||||
# Copyright (c) 2016 Cadence Design Systems, Inc.
|
||||
# Copyright (c) 2019 Intel Corp.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config RISCV_MACHINE_TIMER
|
||||
bool "RISCV Machine Timer"
|
||||
depends on SOC_FAMILY_RISCV_PRIVILEGE
|
||||
select TICKLESS_CAPABLE
|
||||
select TIMER_HAS_64BIT_CYCLE_COUNTER
|
||||
help
|
||||
This module implements a kernel device driver for the generic RISCV machine
|
||||
timer driver. It provides the standard "system clock driver" interfaces.
|
||||
14
drivers/timer/Kconfig.rv32m1_lptmr
Normal file
14
drivers/timer/Kconfig.rv32m1_lptmr
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
# Copyright (c) 2014-2015 Wind River Systems, Inc.
|
||||
# Copyright (c) 2016 Cadence Design Systems, Inc.
|
||||
# Copyright (c) 2019 Intel Corp.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config RV32M1_LPTMR_TIMER
|
||||
bool "RV32M1 LPTMR system timer driver"
|
||||
default y
|
||||
depends on SOC_OPENISA_RV32M1_RISCV32
|
||||
depends on RV32M1_INTMUX
|
||||
help
|
||||
This module implements a kernel device driver for using the LPTMR
|
||||
peripheral as the system clock. It provides the standard "system clock
|
||||
driver" interfaces.
|
||||
13
drivers/timer/Kconfig.sam0_rtc
Normal file
13
drivers/timer/Kconfig.sam0_rtc
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
# Copyright (c) 2014-2015 Wind River Systems, Inc.
|
||||
# Copyright (c) 2016 Cadence Design Systems, Inc.
|
||||
# Copyright (c) 2019 Intel Corp.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SAM0_RTC_TIMER
|
||||
bool "Atmel SAM0 series RTC timer"
|
||||
depends on SOC_FAMILY_SAM0
|
||||
select TICKLESS_CAPABLE
|
||||
help
|
||||
This module implements a kernel device driver for the Atmel SAM0
|
||||
series Real Time Counter and provides the standard "system clock
|
||||
driver" interfaces.
|
||||
22
drivers/timer/Kconfig.xlnx_psttc
Normal file
22
drivers/timer/Kconfig.xlnx_psttc
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
# Copyright (c) 2014-2015 Wind River Systems, Inc.
|
||||
# Copyright (c) 2016 Cadence Design Systems, Inc.
|
||||
# Copyright (c) 2019 Intel Corp.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config XLNX_PSTTC_TIMER
|
||||
bool "Xilinx PS ttc timer support"
|
||||
default y
|
||||
depends on SOC_XILINX_ZYNQMP
|
||||
select TICKLESS_CAPABLE
|
||||
help
|
||||
This module implements a kernel device driver for the Xilinx ZynqMP
|
||||
platform provides the standard "system clock driver" interfaces.
|
||||
If unchecked, no timer will be used.
|
||||
|
||||
config XLNX_PSTTC_TIMER_INDEX
|
||||
int "Xilinx PS ttc timer index"
|
||||
range 0 3
|
||||
default 0
|
||||
depends on XLNX_PSTTC_TIMER
|
||||
help
|
||||
This is the index of TTC timer picked to provide system clock.
|
||||
26
drivers/timer/Kconfig.xtensa
Normal file
26
drivers/timer/Kconfig.xtensa
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
# Copyright (c) 2014-2015 Wind River Systems, Inc.
|
||||
# Copyright (c) 2016 Cadence Design Systems, Inc.
|
||||
# Copyright (c) 2019 Intel Corp.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config XTENSA_TIMER
|
||||
bool "Xtensa timer support"
|
||||
depends on XTENSA
|
||||
default y
|
||||
select TICKLESS_CAPABLE
|
||||
help
|
||||
Enables a system timer driver for Xtensa based on the CCOUNT
|
||||
and CCOMPARE special registers.
|
||||
|
||||
config XTENSA_TIMER_ID
|
||||
int "System timer CCOMPAREn register index"
|
||||
default 1
|
||||
depends on XTENSA_TIMER
|
||||
help
|
||||
Index of the CCOMPARE register (and associated interrupt)
|
||||
used for the system timer. Xtensa CPUs have hard-configured
|
||||
interrupt priorities associated with each timer, and some of
|
||||
them can be unmaskable (and thus not usable by OS code that
|
||||
need synchronization, like the timer subsystem!). Choose
|
||||
carefully. Generally you want the timer with the highest
|
||||
priority maskable interrupt.
|
||||
Loading…
Reference in a new issue