arch/x86/soc: add SoC configuration for Apollo Lake

This adds the SoC configuration for Apollo Lake. This is based
on the Atom configuration.

Origin: Original

Signed-off-by: Daniel Leung <daniel.leung@intel.com>

arch/x86/Kconfig

@@ -47,6 +47,16 @@ config CPU_MINUTEIA
 	help
 	  This option signifies the use of a CPU from the Minute IA family.
 
+config CPU_APOLLO_LAKE
+	# Hidden
+	bool
+	select CMOV
+	select CPU_HAS_FPU
+	select ARCH_HAS_STACK_PROTECTION if X86_MMU
+	select ARCH_HAS_USERSPACE if X86_MMU
+	help
+	  This option signifies the use of a CPU from the Apollo Lake family.
+
 menu "Processor Capabilities"
 
 config X86_IAMCU

arch/x86/soc/apollo_lake/CMakeLists.txt

@@ -0,0 +1,7 @@
+zephyr_library()
+zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
+
+zephyr_cc_option(-march=silvermont)
+zephyr_cc_option_fallback(-march=atom -mtune=silvermont)
+
+zephyr_library_sources(soc.c)

arch/x86/soc/apollo_lake/Kconfig.defconfig

@@ -0,0 +1,49 @@
+#
+# Kconfig - Apollo Lake SoC configuration options
+#
+# Copyright (c) 2018 Intel Corporation
+# Copyright (c) 2014-2015 Wind River Systems, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_APOLLO_LAKE
+
+config SOC
+	default "apollo_lake"
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 150000000 if LOAPIC_TIMER
+	default 25000000  if HPET_TIMER
+
+config CLFLUSH_DETECT
+	def_bool y if CACHE_FLUSHING
+
+if UART_NS16550
+
+config UART_NS16550_PCI
+	def_bool n
+
+config UART_NS16550_PORT_0
+	def_bool y
+
+if UART_NS16550_PORT_0
+
+config UART_NS16550_PORT_0_OPTIONS
+	default 0
+
+endif # UART_NS16550_PORT_0
+
+config UART_NS16550_PORT_1
+	def_bool y
+
+if UART_NS16550_PORT_1
+
+config UART_NS16550_PORT_1_OPTIONS
+	default 0
+
+endif # UART_NS16550_PORT_1
+
+endif # UART_NS16550
+
+endif # SOC_APOLLO_LAKE

arch/x86/soc/apollo_lake/Kconfig.soc

@@ -0,0 +1,10 @@
+#
+# Copyright (c) 2018 Intel Corporation Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SOC_APOLLO_LAKE
+	bool "Intel Apollo Lake Soc"
+	select CPU_APOLLO_LAKE
+	select BOOTLOADER_UNKNOWN

arch/x86/soc/apollo_lake/dts.fixup

@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2018 Intel Corporation Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* SoC level DTS fixup file */
+
+#define CONFIG_PHYS_RAM_ADDR                    CONFIG_SRAM_BASE_ADDRESS
+
+#define CONFIG_PHYS_LOAD_ADDR                   CONFIG_FLASH_BASE_ADDRESS
+
+#define CONFIG_RAM_SIZE                         CONFIG_SRAM_SIZE
+
+#define CONFIG_ROM_SIZE                         CONFIG_FLASH_SIZE
+
+#define CONFIG_IOAPIC_BASE_ADDRESS              INTEL_IOAPIC_FEC00000_BASE_ADDRESS
+
+/* End of SoC Level DTS fixup file */

arch/x86/soc/apollo_lake/linker.ld

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2011-2014, Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Linker command/script file
+ *
+ * This is the linker script for both standard images and XIP images.
+ */
+
+#include <autoconf.h>
+#include <generated_dts_board.h>
+/* physical address where the kernel is loaded */
+#define PHYS_LOAD_ADDR CONFIG_PHYS_LOAD_ADDR
+
+/* physical address of RAM */
+#ifdef CONFIG_XIP
+  #define PHYS_RAM_ADDR    CONFIG_PHYS_RAM_ADDR
+#else  /* !CONFIG_XIP */
+  #define PHYS_RAM_ADDR    PHYS_LOAD_ADDR
+#endif /* CONFIG_XIP */
+
+MEMORY
+    {
+#ifdef CONFIG_XIP
+    ROM (rx)        : ORIGIN = PHYS_LOAD_ADDR, LENGTH = CONFIG_ROM_SIZE*1K
+    RAM (wx)        : ORIGIN = PHYS_RAM_ADDR, LENGTH = CONFIG_RAM_SIZE*1K
+#else  /* !CONFIG_XIP */
+    RAM (wx)	    : ORIGIN = PHYS_LOAD_ADDR, LENGTH = CONFIG_RAM_SIZE*1K
+#endif /* CONFIG_XIP */
+
+    /*
+     * It doesn't matter where this region goes as it is stripped from the
+     * final ELF image. The address doesn't even have to be valid on the
+     * target. However, it shouldn't overlap any other regions.
+     */
+
+    IDT_LIST        : ORIGIN = 2K, LENGTH = 2K
+#ifdef CONFIG_X86_MMU
+    MMU_LIST	    : ORIGIN = 4k, LENGTH = 1K
+#endif
+    }
+
+#include <arch/x86/linker.ld>
+

arch/x86/soc/apollo_lake/soc.c

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2018, Intel Corporation
+ * Copyright (c) 2011-2015, Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for the Apollo Lake SoC
+ *
+ * This module provides routines to initialize and support soc-level hardware
+ * for the Apollo Lake SoC.
+ */
+
+#include <kernel.h>
+#include "soc.h"
+#include <uart.h>
+#include <device.h>
+#include <init.h>
+
+#ifdef CONFIG_X86_MMU
+/* loapic */
+MMU_BOOT_REGION(CONFIG_LOAPIC_BASE_ADDRESS, 4 * 1024, MMU_ENTRY_WRITE);
+
+/* ioapic */
+MMU_BOOT_REGION(CONFIG_IOAPIC_BASE_ADDRESS, 1024 * 1024, MMU_ENTRY_WRITE);
+
+#ifdef CONFIG_HPET_TIMER
+MMU_BOOT_REGION(CONFIG_HPET_TIMER_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE);
+#endif  /* CONFIG_HPET_TIMER */
+
+/* for UARTs */
+#ifdef CONFIG_UART_NS16550
+
+#ifdef CONFIG_UART_NS16550_PORT_0
+MMU_BOOT_REGION(CONFIG_UART_NS16550_PORT_0_BASE_ADDR, 0x1000,
+		(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
+#endif
+
+#ifdef CONFIG_UART_NS16550_PORT_1
+MMU_BOOT_REGION(CONFIG_UART_NS16550_PORT_1_BASE_ADDR, 0x1000,
+		(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
+#endif
+
+#endif  /* CONFIG_UART_NS16550 */
+
+#endif  /* CONFIG_X86_MMU */

arch/x86/soc/apollo_lake/soc.h

@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2018, Intel Corporation
+ * Copyright (c) 2010-2015, Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Board configuration macros for the Apollo Lake SoC
+ *
+ * This header file is used to specify and describe soc-level aspects for
+ * the 'Apollo Lake' SoC.
+ */
+
+#ifndef __SOC_H_
+#define __SOC_H_
+
+#include <misc/util.h>
+
+#ifndef _ASMLANGUAGE
+#include <device.h>
+#include <random/rand32.h>
+#endif
+
+#endif /* __SOC_H_ */

dts/x86/apollo_lake.dtsi

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2017-2018 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/intel-ioapic.h>
+
+#define __SIZE_K(x) (x * 1024)
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "apollo_lake";
+			reg = <0>;
+		};
+
+		intc: ioapic@fec00000  {
+			compatible = "intel,ioapic";
+			reg = <0xfec00000 0x100000>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+		};
+	};
+
+	flash0: flash@100000{
+		reg = <0x00100000 DT_FLASH_SIZE>;
+	};
+
+	sram0: memory@400000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0x00400000 DT_SRAM_SIZE>;
+	};
+
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+	};
+};