boards: arm: fk7b0m1_vbt6: add support to external NOR Flash
Updates the DTS file by adding support for QSPI and SPI NOR Flash. Signed-off-by: Charles Dias <charlesdias.cd@outlook.com>
This commit is contained in:
Charles Dias
Fabio Baltieri
parent
c5b2a16dd2
commit
276dc8c138
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@ -57,7 +57,7 @@ More information about STM32H7B0VB can be found here:
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Supported Features
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==================
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The Zephyr nucleo_h723zg board configuration supports the following hardware
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The Zephyr fk7b0m1_vbt6 board configuration supports the following hardware
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features:
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+-------------+------------+-------------------------------------+
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@ -65,6 +65,8 @@ features:
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+=============+============+=====================================+
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| NVIC | on-chip | nested vector interrupt controller |
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+-------------+------------+-------------------------------------+
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| FLASH | on-chip | flash memory |
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+-------------+------------+-------------------------------------+
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| UART | on-chip | serial port |
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+-------------+------------+-------------------------------------+
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| PINMUX | on-chip | pinmux |
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@ -75,19 +77,20 @@ features:
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+-------------+------------+-------------------------------------+
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| Backup SRAM | on-chip | Backup SRAM |
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+-------------+------------+-------------------------------------+
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| SPI | on-chip | spi bus |
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+-------------+------------+-------------------------------------+
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| OCTOSPI | on-chip | octospi |
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+-------------+------------+-------------------------------------+
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Other hardware features are not yet supported on this Zephyr port.
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The default configuration per core can be found in
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:zephyr_file:`boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6_defconfig`
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Connections and IOs
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===================
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Pin Mapping
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===========
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Available pins:
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---------------
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Nucleo FK7B0M1-VBT6 board has 6 GPIO controllers. These controllers are responsible for pin muxing,
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FK7B0M1-VBT6 board has 5 GPIO controllers. These controllers are responsible for pin muxing,
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input/output, pull-up, etc.
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.. figure:: img/fk7b0m1_vbt6_pins.webp
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@ -97,29 +100,17 @@ input/output, pull-up, etc.
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FK7B0M1-VBT6 (Credit: FANKE Technology Co., Ltd)
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LED
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---
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Default Zephyr Peripheral Mapping:
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----------------------------------
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- User LED (blue) = PC1
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The FK7B0M1-VBT6 board is configured as follows
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Push buttons
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-------------------------
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- BOOT = SW1 = BOOT0
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- RESET = SW2 = NRST
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- User button = SW3 = PC13
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UART
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-----
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- TX device = USART1 PA9
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- RX device = USART1 PA10
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USB
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---
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- USB D- = PA11
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- USB D+ = PA12
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- UART_1 TX/RX : PA9/PA10 (available on the header pins)
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- User LED (blue) : PC1
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- User PB : PC13
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- SPI1 NCS/CLK/MISO/MOSI : PA15/PB3/PB4/PB5 (NOR Flash)
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- QuadSPI NCS/CLK/IO0/IO1/IO2/IO3 : PB6/PB2/PD11/PD12/PE2/PD13 (NOR Flash)
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- USB DM/DP : PA11/PA12
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System Clock
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============
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@ -136,13 +127,19 @@ The Zephyr console output is assigned to UART1. The default communication settin
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Programming and Debugging
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*************************
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Applications for the ``fk7b0m1_vbt6`` board configuration can be built and flashed in the usual
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way (see :ref:`build_an_application` and :ref:`application_run` for more details).
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Flashing
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========
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The FK7B0M1-VBT6 board does not include an on-board debugger. As a result, it requires
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an external debugger, such as ST-Link, for programming and debugging purposes.
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The board provides header pins for the Serial Wire Debug (SWD) interface.
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Flashing
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========
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Flashing an application to FK7B0M1-VBT6
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---------------------------------------
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To begin, connect the ST-Link Debug Programmer to the FK7B0M1-VBT6 board using the SWD
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interface. Next, connect the ST-Link to your host computer via a USB port.
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@ -41,6 +41,7 @@
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aliases {
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led0 = &user_led;
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sw0 = &user_button;
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spi-flash0 = &w25q64jvssiq_spi;
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};
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};
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@ -75,6 +76,60 @@
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d3ppre = <2>;
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};
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&octospi1 {
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pinctrl-0 = <&octospim_p1_clk_pb2 &octospim_p1_ncs_pb6
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&octospim_p1_io0_pd11 &octospim_p1_io1_pd12
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&octospim_p1_io2_pe2 &octospim_p1_io3_pd13>;
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pinctrl-names = "default";
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status = "okay";
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/* Winbond external flash */
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w25q64jvssiq_qspi: qspi-nor-flash@0 {
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compatible = "st,stm32-ospi-nor";
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reg = <0 DT_SIZE_M(8)>; /* 64 Mbits */
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ospi-max-frequency = <DT_FREQ_M(133)>;
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spi-bus-width = <OSPI_QUAD_MODE>;
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data-rate = <OSPI_STR_TRANSFER>;
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writeoc = "PP_1_1_4";
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status = "okay";
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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slot0_partition: partition@0 {
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reg = <0x00000000 DT_SIZE_M(8)>; /* 64 Mbits */
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};
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};
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};
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};
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&spi6 {
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pinctrl-0 = <&spi6_sck_pb3 &spi6_miso_pb4 &spi6_mosi_pb5>;
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cs-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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status = "okay";
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w25q64jvssiq_spi: spi-nor-flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <DT_FREQ_M(40)>;
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size = <DT_SIZE_M(64)>; /* 64 Mbits */
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status = "okay";
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jedec-id = [ef 40 17];
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has-dpd;
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t-enter-dpd = <3500>;
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t-exit-dpd = <3500>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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storage_partition: partition@0 {
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label = "storage";
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reg = <0x00000000 DT_SIZE_M(8)>; /* 64 Mbits */
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};
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};
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};
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};
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&usart1 {
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pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
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pinctrl-names = "default";
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