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arch: arc: fix the bug of IRQ_ACT.U bit sync up

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This bug is brought in commit 3f88ddd54999.

The cleanup of IRQ_ACT.U bit before thread switch is not done.

The bug comes out at the case where interrupt comes in user mode,
then a thread switch happens, and the target thread is to run in kernel
mode. Because the U bit is not sync up correctly, the stack operation
is wrong.

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
This commit is contained in:
Wayne Ren 2020-04-11 15:33:06 +08:00 committed by Andrew Boie
parent 1f3c014a1a
commit 2833d016aa
1 changed files with 11 additions and 18 deletions
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29
arch/arc/include/swap_macros.h
View file

@ -407,12 +407,21 @@
.macro _irq_store_old_thread_callee_regs .macro _irq_store_old_thread_callee_regs
#if defined(CONFIG_USERSPACE) #if defined(CONFIG_USERSPACE)
/* /*
* when USERSPACE is enabled, according to ARCv2 ISA, SP will be switched
* if interrupt comes out in user mode, and will be recorded in bit 31
* (U bit) of IRQ_ACT. when interrupt exits, SP will be switched back
* according to U bit.
*
* need to remember the user/kernel status of interrupted thread, will be * need to remember the user/kernel status of interrupted thread, will be
* restored when thread switched back * restored when thread switched back
*
*/ */
lr r3, [_ARC_V2_AUX_IRQ_ACT] lr r1, [_ARC_V2_AUX_IRQ_ACT]
and r3, r3, 0x80000000 and r3, r1, 0x80000000
push_s r3 push_s r3
bclr r1, r1, 31
sr r1, [_ARC_V2_AUX_IRQ_ACT]
#endif #endif
_store_old_thread_callee_regs _store_old_thread_callee_regs
.endm .endm
@ -440,22 +449,6 @@
/* when switch to thread caused by coop, some status regs need to set */ /* when switch to thread caused by coop, some status regs need to set */
.macro _set_misc_regs_irq_switch_from_coop .macro _set_misc_regs_irq_switch_from_coop
#if defined(CONFIG_USERSPACE)
/*
* when USERSPACE is enabled, according to ARCv2 ISA, SP will be switched
* if interrupt comes out in user mode, and will be recorded in bit 31
* (U bit) of IRQ_ACT. when interrupt exits, SP will be switched back
* according to U bit.
*
* For the case that context switches in interrupt, the target sp must be
* thread's kernel stack, no need to do hardware sp switch. so, U bit should
* be cleared.
*/
lr r0, [_ARC_V2_AUX_IRQ_ACT]
bclr r0, r0, 31
sr r0, [_ARC_V2_AUX_IRQ_ACT]
#endif
#ifdef CONFIG_ARC_SECURE_FIRMWARE #ifdef CONFIG_ARC_SECURE_FIRMWARE
/* must return to secure mode, so set IRM bit to 1 */ /* must return to secure mode, so set IRM bit to 1 */
lr r0, [_ARC_V2_SEC_STAT] lr r0, [_ARC_V2_SEC_STAT]