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drivers: clock_control: clock driver for Intel Agilex5 platform

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This is Intel's proprietary IP which supply the clock for all the
system peripherals. Clock manager is initialized only one time
during boot up by FSBL (ATF BL2) based on external user settings.

Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
This commit is contained in:
Girisha Dengi 2023-07-06 14:09:24 +00:00 committed by Fabio Baltieri
parent 42477ed68d
commit 2ca6ffcd79
8 changed files with 459 additions and 0 deletions
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2
drivers/clock_control/CMakeLists.txt
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@ -62,6 +62,8 @@ endif()
zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_AGILEX clock_agilex_ll.c)
zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_AGILEX clock_agilex.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_AGILEX5 clock_control_agilex5_ll.c)
zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_AGILEX5 clock_control_agilex5.c)
if(CONFIG_CLOCK_CONTROL_RCAR_CPG_MSSR)
zephyr_library_sources(clock_control_renesas_cpg_mssr.c)

2
drivers/clock_control/Kconfig
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@ -78,4 +78,6 @@ source "drivers/clock_control/Kconfig.numaker"
source "drivers/clock_control/Kconfig.nxp_s32"
source "drivers/clock_control/Kconfig.agilex5"
endif # CLOCK_CONTROL

9
drivers/clock_control/Kconfig.agilex5 Normal file
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@ -0,0 +1,9 @@
# Copyright (C) 2023, Intel Corporation
# SPDX-License-Identifier: Apache-2.0
config CLOCK_CONTROL_AGILEX5
bool "Agilex5 SoCFPGA clock control driver"
default y
depends on DT_HAS_INTEL_AGILEX5_CLOCK_ENABLED
help
This option enables the clock driver for Intel Agilex5 SoCFPGA SOC.

86
drivers/clock_control/clock_control_agilex5.c Normal file
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@ -0,0 +1,86 @@
/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright (C) 2022-2023, Intel Corporation
*
*/
#include <zephyr/drivers/clock_control.h>
#include <zephyr/dt-bindings/clock/intel_socfpga_clock.h>
#include <zephyr/logging/log.h>
#include "clock_control_agilex5_ll.h"
#define DT_DRV_COMPAT intel_agilex5_clock
LOG_MODULE_REGISTER(clock_control_agilex5, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
struct clock_control_config {
DEVICE_MMIO_ROM;
};
struct clock_control_data {
DEVICE_MMIO_RAM;
};
static int clock_init(const struct device *dev)
{
DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
/* Initialize the low layer clock driver */
clock_agilex5_ll_init(DEVICE_MMIO_GET(dev));
LOG_INF("Intel Agilex5 clock driver initialized!");
return 0;
}
static int clock_get_rate(const struct device *dev, clock_control_subsys_t sub_system,
uint32_t *rate)
{
ARG_UNUSED(dev);
switch ((intptr_t)sub_system) {
case INTEL_SOCFPGA_CLOCK_MPU:
*rate = get_mpu_clk();
break;
case INTEL_SOCFPGA_CLOCK_WDT:
*rate = get_wdt_clk();
break;
case INTEL_SOCFPGA_CLOCK_UART:
*rate = get_uart_clk();
break;
case INTEL_SOCFPGA_CLOCK_MMC:
*rate = get_mmc_clk();
break;
case INTEL_SOCFPGA_CLOCK_TIMER:
*rate = get_timer_clk();
break;
default:
LOG_ERR("Clock ID %ld is not supported\n", (intptr_t)sub_system);
return -ENOTSUP;
}
return 0;
}
static const struct clock_control_driver_api clock_api = {.get_rate = clock_get_rate};
#define CLOCK_CONTROL_DEVICE(_inst) \
\
static struct clock_control_data clock_control_data_##_inst; \
\
static const struct clock_control_config clock_control_config_##_inst = { \
DEVICE_MMIO_ROM_INIT(DT_DRV_INST(_inst)), \
}; \
\
DEVICE_DT_INST_DEFINE(_inst, clock_init, NULL, &clock_control_data_##_inst, \
&clock_control_config_##_inst, PRE_KERNEL_1, \
CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &clock_api);
DT_INST_FOREACH_STATUS_OKAY(CLOCK_CONTROL_DEVICE)

181
drivers/clock_control/clock_control_agilex5_ll.c Normal file
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@ -0,0 +1,181 @@
/*
* Copyright (c) 2022-2023, Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <socfpga_system_manager.h>
#include "clock_control_agilex5_ll.h"
LOG_MODULE_REGISTER(clock_control_agilex5_ll, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
/* Clock manager individual group base addresses. */
struct clock_agilex5_ll_params {
mm_reg_t base_addr;
mm_reg_t mainpll_addr;
mm_reg_t peripll_addr;
mm_reg_t ctl_addr;
};
/* Clock manager low layer(ll) params object. */
static struct clock_agilex5_ll_params clock_agilex5_ll;
/* Initialize the clock ll with the given base address */
void clock_agilex5_ll_init(mm_reg_t base_addr)
{
/* Clock manager module base address. */
clock_agilex5_ll.base_addr = base_addr;
/* Clock manager main PLL base address. */
clock_agilex5_ll.mainpll_addr = clock_agilex5_ll.base_addr + CLKMGR_MAINPLL_OFFSET;
/* Clock manager peripheral PLL base address. */
clock_agilex5_ll.peripll_addr = clock_agilex5_ll.base_addr + CLKMGR_PERPLL_OFFSET;
/* Clock manager control module base address. */
clock_agilex5_ll.ctl_addr = clock_agilex5_ll.base_addr + CLKMGR_INTEL_OFFSET;
}
/* Extract reference clock from platform clock source */
static uint32_t get_ref_clk(uint32_t pllglob)
{
uint32_t arefclkdiv, ref_clk;
uint32_t scr_reg;
/*
* Based on the clock source, read the values from System Manager boot
* scratch registers. These values are filled by boot loader based on
* hand-off data.
*/
switch (CLKMGR_PSRC(pllglob)) {
case CLKMGR_PLLGLOB_PSRC_EOSC1:
scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1);
ref_clk = sys_read32(scr_reg);
break;
case CLKMGR_PLLGLOB_PSRC_INTOSC:
ref_clk = CLKMGR_INTOSC_HZ;
break;
case CLKMGR_PLLGLOB_PSRC_F2S:
scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2);
ref_clk = sys_read32(scr_reg);
break;
default:
ref_clk = 0;
LOG_ERR("Invalid VCO input clock source");
break;
}
/* Reference clock divider, to get the effective reference clock. */
arefclkdiv = CLKMGR_PLLGLOB_AREFCLKDIV(pllglob);
ref_clk /= arefclkdiv;
return ref_clk;
}
/* Calculate clock frequency based on parameter */
static uint32_t get_clk_freq(uint32_t psrc_reg, uint32_t main_pllc, uint32_t per_pllc)
{
uint32_t clk_psrc, mdiv, ref_clk;
uint32_t pllm_reg, pllc_reg, pllc_div, pllglob_reg;
clk_psrc = sys_read32(clock_agilex5_ll.mainpll_addr + psrc_reg);
switch (CLKMGR_PSRC(clk_psrc)) {
case CLKMGR_PSRC_MAIN:
pllm_reg = clock_agilex5_ll.mainpll_addr + CLKMGR_MAINPLL_PLLM;
pllc_reg = clock_agilex5_ll.mainpll_addr + main_pllc;
pllglob_reg = clock_agilex5_ll.mainpll_addr + CLKMGR_MAINPLL_PLLGLOB;
break;
case CLKMGR_PSRC_PER:
pllm_reg = clock_agilex5_ll.peripll_addr + CLKMGR_PERPLL_PLLM;
pllc_reg = clock_agilex5_ll.peripll_addr + per_pllc;
pllglob_reg = clock_agilex5_ll.peripll_addr + CLKMGR_PERPLL_PLLGLOB;
break;
default:
return 0;
}
ref_clk = get_ref_clk(sys_read32(pllglob_reg));
mdiv = CLKMGR_PLLM_MDIV(sys_read32(pllm_reg));
ref_clk *= mdiv;
/* Clock slice divider ration in binary code. */
pllc_div = CLKMGR_PLLC_DIV(sys_read32(pllc_reg));
return ref_clk / pllc_div;
}
/* Return L3 interconnect clock */
uint32_t get_l3_clk(void)
{
uint32_t l3_clk;
l3_clk = get_clk_freq(CLKMGR_MAINPLL_NOCCLK, CLKMGR_MAINPLL_PLLC1, CLKMGR_PERPLL_PLLC1);
return l3_clk;
}
/* Calculate clock frequency to be used for mpu */
uint32_t get_mpu_clk(void)
{
uint32_t mpu_clk;
mpu_clk = get_clk_freq(CLKMGR_MAINPLL_MPUCLK, CLKMGR_MAINPLL_PLLC0, CLKMGR_PERPLL_PLLC0);
return mpu_clk;
}
/* Calculate clock frequency to be used for watchdog timer */
uint32_t get_wdt_clk(void)
{
uint32_t l4_sys_clk;
l4_sys_clk = (get_l3_clk() >> 2);
return l4_sys_clk;
}
/* Calculate clock frequency to be used for UART driver */
uint32_t get_uart_clk(void)
{
uint32_t mainpll_nocdiv, l4_sp_clk;
mainpll_nocdiv = sys_read32(clock_agilex5_ll.mainpll_addr + CLKMGR_MAINPLL_NOCDIV);
mainpll_nocdiv = CLKMGR_MAINPLL_L4SPDIV(mainpll_nocdiv);
l4_sp_clk = (get_l3_clk() >> mainpll_nocdiv);
return l4_sp_clk;
}
/* Calculate clock frequency to be used for SDMMC driver */
uint32_t get_mmc_clk(void)
{
uint32_t sdmmc_ctr, mmc_clk;
mmc_clk = get_clk_freq(CLKMGR_INTEL_SDMMCCTR, CLKMGR_MAINPLL_PLLC3, CLKMGR_PERPLL_PLLC3);
sdmmc_ctr = sys_read32(clock_agilex5_ll.ctl_addr + CLKMGR_INTEL_SDMMCCTR);
sdmmc_ctr = CLKMGR_INTEL_SDMMC_CNT(sdmmc_ctr);
mmc_clk = ((mmc_clk / sdmmc_ctr) >> 2);
return mmc_clk;
}
/* Calculate clock frequency to be used for Timer driver */
uint32_t get_timer_clk(void)
{
uint32_t l4_sys_clk;
l4_sys_clk = (get_l3_clk() >> 2);
return l4_sys_clk;
}

160
drivers/clock_control/clock_control_agilex5_ll.h Normal file
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@ -0,0 +1,160 @@
/*
* Copyright (c) 2022-2023, Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_AGILEX5_LL_H_
#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_AGILEX5_LL_H_
#include <stdint.h>
#include <zephyr/sys/sys_io.h>
/* Clock manager register offsets */
#define CLKMGR_CTRL 0x00
#define CLKMGR_STAT 0x04
#define CLKMGR_INTRCLR 0x14
/* Clock manager main PLL group register offsets */
#define CLKMGR_MAINPLL_OFFSET 0x24
#define CLKMGR_MAINPLL_EN 0x00
#define CLKMGR_MAINPLL_BYPASS 0x0C
#define CLKMGR_MAINPLL_MPUCLK 0x18
#define CLKMGR_MAINPLL_BYPASSS 0x10
#define CLKMGR_MAINPLL_NOCCLK 0x1C
#define CLKMGR_MAINPLL_NOCDIV 0x20
#define CLKMGR_MAINPLL_PLLGLOB 0x24
#define CLKMGR_MAINPLL_FDBCK 0x28
#define CLKMGR_MAINPLL_MEM 0x2C
#define CLKMGR_MAINPLL_MEMSTAT 0x30
#define CLKMGR_MAINPLL_VCOCALIB 0x34
#define CLKMGR_MAINPLL_PLLC0 0x38
#define CLKMGR_MAINPLL_PLLC1 0x3C
#define CLKMGR_MAINPLL_PLLC2 0x40
#define CLKMGR_MAINPLL_PLLC3 0x44
#define CLKMGR_MAINPLL_PLLM 0x48
#define CLKMGR_MAINPLL_LOSTLOCK 0x54
/* Clock manager peripheral PLL group register offsets */
#define CLKMGR_PERPLL_OFFSET 0x7C
#define CLKMGR_PERPLL_EN 0x00
#define CLKMGR_PERPLL_BYPASS 0x0C
#define CLKMGR_PERPLL_BYPASSS 0x10
#define CLKMGR_PERPLL_EMACCTL 0x18
#define CLKMGR_PERPLL_GPIODIV 0x1C
#define CLKMGR_PERPLL_PLLGLOB 0x20
#define CLKMGR_PERPLL_FDBCK 0x24
#define CLKMGR_PERPLL_MEM 0x28
#define CLKMGR_PERPLL_MEMSTAT 0x2C
#define CLKMGR_PERPLL_VCOCALIB 0x30
#define CLKMGR_PERPLL_PLLC0 0x34
#define CLKMGR_PERPLL_PLLC1 0x38
#define CLKMGR_PERPLL_PLLC2 0x3C
#define CLKMGR_PERPLL_PLLC3 0x40
#define CLKMGR_PERPLL_PLLM 0x44
#define CLKMGR_PERPLL_LOSTLOCK 0x50
/* Clock manager control/intel group register offsets */
#define CLKMGR_INTEL_OFFSET 0xD0
#define CLKMGR_INTEL_JTAG 0x00
#define CLKMGR_INTEL_EMACACTR 0x4
#define CLKMGR_INTEL_EMACBCTR 0x8
#define CLKMGR_INTEL_EMACPTPCTR 0x0C
#define CLKMGR_INTEL_GPIODBCTR 0x10
#define CLKMGR_INTEL_SDMMCCTR 0x14
#define CLKMGR_INTEL_S2FUSER0CTR 0x18
#define CLKMGR_INTEL_S2FUSER1CTR 0x1C
#define CLKMGR_INTEL_PSIREFCTR 0x20
#define CLKMGR_INTEL_EXTCNTRST 0x24
/* Clock manager macros */
#define CLKMGR_CTRL_BOOTMODE_SET_MSK 0x00000001U
#define CLKMGR_STAT_BUSY_E_BUSY 0x1
#define CLKMGR_STAT_BUSY(x) (((x) & 0x00000001U) >> 0)
#define CLKMGR_STAT_MAINPLLLOCKED(x) (((x) & 0x00000100U) >> 8)
#define CLKMGR_STAT_PERPLLLOCKED(x) (((x) & 0x00010000U) >> 16)
#define CLKMGR_INTRCLR_MAINLOCKLOST_SET_MSK 0x00000004U
#define CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK 0x00000008U
#define CLKMGR_MAINPLL_L4SPDIV(x) (((x) >> 16) & 0x3)
#define CLKMGR_INTOSC_HZ 460000000U
/* Shared Macros */
#define CLKMGR_PSRC(x) (((x) & 0x00030000U) >> 16)
#define CLKMGR_PSRC_MAIN 0
#define CLKMGR_PSRC_PER 1
#define CLKMGR_PLLGLOB_PSRC_EOSC1 0x0
#define CLKMGR_PLLGLOB_PSRC_INTOSC 0x1
#define CLKMGR_PLLGLOB_PSRC_F2S 0x2
#define CLKMGR_PLLM_MDIV(x) ((x) & 0x000003FFU)
#define CLKMGR_PLLGLOB_PD_SET_MSK 0x00000001U
#define CLKMGR_PLLGLOB_RST_SET_MSK 0x00000002U
#define CLKMGR_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003F00) >> 8)
#define CLKMGR_PLLGLOB_AREFCLKDIV(x) (((x) & 0x00000F00) >> 8)
#define CLKMGR_PLLGLOB_DREFCLKDIV(x) (((x) & 0x00003000) >> 12)
#define CLKMGR_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000003FF)
#define CLKMGR_VCOCALIB_MSCNT_SET(x) (((x) << 16) & 0x00FF0000)
#define CLKMGR_CLR_LOSTLOCK_BYPASS 0x20000000U
#define CLKMGR_PLLC_DIV(x) ((x) & 0x7FF)
#define CLKMGR_INTEL_SDMMC_CNT(x) (((x) & 0x7FF) + 1)
/**
* @brief Initialize the low layer clock control driver
*
* @param base_addr : Clock control device MMIO base address
*
* @return void
*/
void clock_agilex5_ll_init(mm_reg_t base_addr);
/**
* @brief Get MPU(Micro Processor Unit) clock value
*
* @param void
*
* @return returns MPU clock value
*/
uint32_t get_mpu_clk(void);
/**
* @brief Get Watchdog peripheral clock value
*
* @param void
*
* @return returns Watchdog clock value
*/
uint32_t get_wdt_clk(void);
/**
* @brief Get UART peripheral clock value
*
* @param void
*
* @return returns UART clock value
*/
uint32_t get_uart_clk(void);
/**
* @brief Get MMC peripheral clock value
*
* @param void
*
* @return returns MMC clock value
*/
uint32_t get_mmc_clk(void);
/**
* @brief Get Timer peripheral clock value
*
* @param void
*
* @return returns Timer clock value
*/
uint32_t get_timer_clk(void);
#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_AGILEX5_LL_H_ */

18
dts/bindings/clock/intel,agilex5-clock.yaml Normal file
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@ -0,0 +1,18 @@
# Copyright (c) 2023, Intel Corporation
# SPDX-License-Identifier: Apache-2.0
description: Agilex5 clock controller node
compatible: "intel,agilex5-clock"
include: [clock-controller.yaml, base.yaml]
properties:
reg:
required: true
"#clock-cells":
const: 1
clock-cells:
- clkid

1
include/zephyr/dt-bindings/clock/intel_socfpga_clock.h
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@ -12,5 +12,6 @@
#define INTEL_SOCFPGA_CLOCK_WDT 1
#define INTEL_SOCFPGA_CLOCK_UART 2
#define INTEL_SOCFPGA_CLOCK_MMC 3
#define INTEL_SOCFPGA_CLOCK_TIMER 4
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_INTEL_SOCFPGA_CLOCK_H_ */