drivers: serial: ns16550: Add support for Async APIs
Added support for async APIs for ns16550. This will be enabled by kconfig CONFIG_UART_ASYNC_API. Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
This commit is contained in:
Anisetti Avinash Krishna
Fabio Baltieri
parent
3d5de8920b
commit
2d03aaf99f
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@ -6,6 +6,7 @@ menuconfig UART_NS16550
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depends on DT_HAS_NS16550_ENABLED
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select SERIAL_HAS_DRIVER
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select SERIAL_SUPPORT_INTERRUPT
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select SERIAL_SUPPORT_ASYNC
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help
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This option enables the NS16550 serial driver.
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This driver can be used for the serial hardware
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@ -66,6 +66,7 @@ BUILD_ASSERT(IS_ENABLED(CONFIG_PCIE), "NS16550(s) in DT need CONFIG_PCIE");
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#define REG_MDC 0x04 /* Modem control reg. */
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#define REG_LSR 0x05 /* Line status reg. */
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#define REG_MSR 0x06 /* Modem status reg. */
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#define REG_SCR 0x07 /* Scratchpad. */
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#define REG_DLF 0xC0 /* Divisor Latch Fraction */
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#define REG_PCP 0x200 /* PRV_CLOCK_PARAMS (Apollo Lake) */
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@ -142,6 +143,18 @@ BUILD_ASSERT(IS_ENABLED(CONFIG_PCIE), "NS16550(s) in DT need CONFIG_PCIE");
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*/
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#define FCR_FIFO_64 0x20 /* Enable 64 bytes FIFO */
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/* FIFO Depth. */
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#if defined(CONFIG_UART_NS16550_VARIANT_NS16750)
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#define UART_FIFO_DEPTH (64)
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#elif defined(CONFIG_UART_NS16550_VARIANT_NS16950)
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#define UART_FIFO_DEPTH (128)
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#else
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#define UART_FIFO_DEPTH (16)
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#endif
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/* FIFO Half Depth. */
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#define UART_FIFO_HALF_DEPTH (UART_FIFO_DEPTH / 2)
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/* constants for line control register */
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#define LCR_CS5 0x00 /* 5 bits data size */
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@ -177,6 +190,18 @@ BUILD_ASSERT(IS_ENABLED(CONFIG_PCIE), "NS16550(s) in DT need CONFIG_PCIE");
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#define LSR_THRE 0x20 /* transmit holding register empty */
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#define LSR_TEMT 0x40 /* transmitter empty */
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/* Transfer Error */
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#define UART_PASS 0 /* Transfer completed */
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#define UART_ERROR_CANCELED -ECANCELED /* Operation was canceled */
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#define UART_DRIVER_ERROR -ENOTSUP /* Unsupported error */
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/* Transfer Status */
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#define UART_TRANSFER_SUCCESS 0 /* Transfer success */
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#define UART_TRANSFER_FAILED -EPERM /* Transfer failed */
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/* SCR bit to indicate updated status for LSR. */
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#define UART_SCR_STATUS_UPDATE BIT(0)
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/* constants for modem status register */
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#define MSR_DCTS 0x01 /* cts change */
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@ -199,11 +224,44 @@ BUILD_ASSERT(IS_ENABLED(CONFIG_PCIE), "NS16550(s) in DT need CONFIG_PCIE");
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#define MDC(dev) (get_port(dev) + REG_MDC * reg_interval(dev))
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#define LSR(dev) (get_port(dev) + REG_LSR * reg_interval(dev))
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#define MSR(dev) (get_port(dev) + REG_MSR * reg_interval(dev))
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#define SCR(dev) (get_port(dev) + REG_SCR * reg_interval(dev))
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#define DLF(dev) (get_port(dev) + REG_DLF)
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#define PCP(dev) (get_port(dev) + REG_PCP)
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#define IIRC(dev) (((struct uart_ns16550_dev_data *)(dev)->data)->iir_cache)
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#if CONFIG_UART_ASYNC_API
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/* Macro to get tx semamphore */
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#define GET_TX_SEM(dev) \
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(((const struct uart_ns16550_device_config *) \
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dev->config)->tx_sem)
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/* Macro to get rx sempahore */
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#define GET_RX_SEM(dev) \
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(((const struct uart_ns16550_device_config *) \
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dev->config)->rx_sem)
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/**
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* UART asynchronous transfer structure.
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*/
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struct uart_ns16550_transfer_t {
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uint8_t *data; /**< Pre-allocated write or read buffer. */
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uint32_t data_len; /**< Number of bytes to transfer. */
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/** Transfer callback
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*
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* @param[in] data Callback user data.
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* @param[in] UART_PASS on success,negative value for possible
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* errors.
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* @param[in] status UART module status.To be interpreted with
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* intel_uart_status_t for different error bits.
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* @param[in] len Length of the UART transfer if successful, 0
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* otherwise.
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*/
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void (*callback)(void *data, int error, uint32_t status, uint32_t len);
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void *callback_data; /**< Callback identifier. */
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};
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#endif /* CONFIG_UART_ASYNC_API */
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/* device config */
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struct uart_ns16550_device_config {
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union {
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@ -226,6 +284,12 @@ struct uart_ns16550_device_config {
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#if defined(CONFIG_PINCTRL)
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const struct pinctrl_dev_config *pincfg;
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#endif
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#ifdef CONFIG_UART_ASYNC_API
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struct k_sem *tx_sem;
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struct k_sem *rx_sem;
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#endif
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#if defined(CONFIG_UART_NS16550_ACCESS_IOPORT) || defined(CONFIG_UART_NS16550_SIMULT_ACCESS)
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bool io_map;
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#endif
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@ -251,8 +315,21 @@ struct uart_ns16550_dev_data {
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#if defined(CONFIG_UART_INTERRUPT_DRIVEN) && defined(CONFIG_PM)
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bool tx_stream_on;
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#endif
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#ifdef CONFIG_UART_ASYNC_API
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struct uart_event evt;
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uart_callback_t async_cb;
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void *async_user_data;
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struct uart_ns16550_transfer_t *rx_transfer;
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struct uart_ns16550_transfer_t *tx_transfer;
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uint32_t write_pos;
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uint32_t read_pos;
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#endif
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};
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static void ns16550_outbyte(const struct uart_ns16550_device_config *cfg,
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uintptr_t port, uint8_t val)
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{
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@ -434,7 +511,7 @@ static int uart_ns16550_configure(const struct device *dev,
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}
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clock_control_get_rate(dev_cfg->clock_dev, dev_cfg->clock_subsys,
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&pclk);
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&pclk);
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}
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set_baud_rate(dev, cfg->baudrate, pclk);
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@ -993,6 +1070,221 @@ static void uart_ns16550_irq_callback_set(const struct device *dev,
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k_spin_unlock(&dev_data->lock, key);
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}
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#ifdef CONFIG_UART_ASYNC_API
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static bool is_async_write_complete(const struct device *dev)
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{
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struct uart_ns16550_dev_data * const dev_data = dev->data;
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struct uart_ns16550_transfer_t *transfer = dev_data->tx_transfer;
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return dev_data->write_pos >= transfer->data_len;
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}
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static bool is_async_read_complete(const struct device *dev)
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{
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struct uart_ns16550_dev_data * const dev_data = dev->data;
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struct uart_ns16550_transfer_t *transfer = dev_data->rx_transfer;
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return dev_data->read_pos >= transfer->data_len;
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}
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static void ns16550_write_transfer(const struct device *dev,
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struct uart_ns16550_transfer_t *write_transfer)
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{
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struct uart_ns16550_dev_data * const dev_data = dev->data;
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const struct uart_ns16550_device_config * const dev_cfg = dev->config;
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int count;
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if (!write_transfer) {
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return;
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}
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if (is_async_write_complete(dev)) {
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ns16550_outbyte(dev_cfg, IER(dev),
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ns16550_inbyte(dev_cfg, IER(dev)) & (~IER_TBE));
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/*
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* At this point the FIFOs are empty, but the shift
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* register still is transmitting the last 8 bits.
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* So if we were to read LSR, it would say the device
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* is still busy.
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* Use the SCR Bit 0 to indicate an irq tx is complete.
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*/
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ns16550_outbyte(dev_cfg, SCR(dev), ns16550_inbyte(dev_cfg, SCR(dev))
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| UART_SCR_STATUS_UPDATE);
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if (write_transfer->callback) {
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write_transfer->callback(write_transfer->callback_data,
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UART_PASS, UART_TRANSFER_SUCCESS,
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dev_data->write_pos);
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write_transfer->callback = NULL;
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}
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return;
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}
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/*
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* If we are starting the transfer then the TX FIFO is empty.
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* In that case we set 'count' variable to UART_FIFO_DEPTH
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* in order to take advantage of the whole FIFO capacity.
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*/
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count = (dev_data->write_pos == 0)
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? UART_FIFO_DEPTH
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: UART_FIFO_HALF_DEPTH;
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while (count-- && !is_async_write_complete(dev)) {
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ns16550_outbyte(dev_cfg, THR(dev),
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write_transfer->data[dev_data->write_pos++]);
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}
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/*
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* Change the threshold level to trigger an interrupt when the
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* TX buffer is empty.
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*/
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if (is_async_write_complete(dev)) {
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ns16550_outbyte(dev_cfg, FCR(dev), ns16550_inbyte(dev_cfg, FCR(dev)) |
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(ns16550_inbyte(dev_cfg, IER(dev)) | IER_TBE));
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}
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}
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static void ns16550_read_transfer(const struct device *dev,
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struct uart_ns16550_transfer_t *read_transfer)
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{
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struct uart_ns16550_dev_data * const dev_data = dev->data;
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const struct uart_ns16550_device_config * const dev_cfg = dev->config;
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int lsr;
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if (!read_transfer) {
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return;
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}
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/*
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* Copy data from RX FIFO to xfer buffer as long as the xfer
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* has not completed and we have data in the RX FIFO.
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*/
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while (!is_async_read_complete(dev)) {
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lsr = ns16550_inbyte(dev_cfg, LSR(dev));
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/*
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* A break condition may cause a line status
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* interrupt to follow very closely after a
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* char timeout interrupt, but reading the lsr
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* effectively clears the pending interrupts so
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* we issue here the callback
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* instead, otherwise we would miss it.
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* NOTE: Returned len is 0 for now, this might
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* change in the future.
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*/
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if (lsr & LSR_EOB_MASK) {
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ns16550_outbyte(dev_cfg, IER(dev),
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ns16550_inbyte(dev_cfg, IER(dev)) &
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~(IER_RXRDY | IER_LSR));
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if (read_transfer->callback) {
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read_transfer->callback(read_transfer
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->callback_data,
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UART_DRIVER_ERROR,
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lsr & LSR_EOB_MASK, 0);
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read_transfer->callback = NULL;
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}
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return;
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}
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if (lsr & LSR_RXRDY) {
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read_transfer->data[dev_data->read_pos++] =
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ns16550_inbyte(dev_cfg, THR(dev));
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} else {
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/* No more data in the RX FIFO. */
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break;
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}
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}
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if (is_async_read_complete(dev)) {
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/*
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* Disable both 'Receiver Data Available' and
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* 'Receiver Line Status' interrupts.
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*/
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ns16550_outbyte(dev_cfg, IER(dev), ns16550_inbyte(dev_cfg, IER(dev)) &
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~(IER_RXRDY | IER_LSR));
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if (read_transfer->callback) {
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read_transfer->callback(read_transfer->callback_data,
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UART_PASS, UART_TRANSFER_SUCCESS,
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dev_data->read_pos);
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read_transfer->callback = NULL;
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}
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}
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}
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static void ns16550_line_status(const struct device *dev, uint32_t line_status,
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struct uart_ns16550_transfer_t *read_transfer)
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{
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const struct uart_ns16550_device_config * const dev_cfg = dev->config;
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if (!line_status) {
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return;
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}
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if (read_transfer) {
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ns16550_outbyte(dev_cfg, IER(dev), ns16550_inbyte(dev_cfg, IER(dev)) &
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~(IER_RXRDY | IER_LSR));
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if (read_transfer->callback) {
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/*
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* Return the number of bytes read
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* a zero as a line status error
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* was detected.
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*/
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read_transfer->callback(read_transfer->callback_data,
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UART_DRIVER_ERROR,
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line_status, 0);
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read_transfer->callback = NULL;
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}
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}
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}
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static void uart_ns16550_callback(const struct device *dev)
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{
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struct uart_ns16550_dev_data * const dev_data = dev->data;
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const struct uart_ns16550_device_config * const dev_cfg = dev->config;
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struct uart_ns16550_transfer_t *write_transfer = dev_data->tx_transfer;
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struct uart_ns16550_transfer_t *read_transfer = dev_data->rx_transfer;
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uint8_t interrupt_id = ns16550_inbyte(dev_cfg, IIR(dev)) & IIR_MASK;
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uint32_t line_status;
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/*
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* Interrupt ID priority levels (from highest to lowest):
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* 1: IIR_LS
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* 2: IIR_RBRF and IIR_CH
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* 3: IIR_THRE
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*/
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switch (interrupt_id) {
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/* Spurious interrupt */
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case IIR_NIP:
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break;
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case IIR_LS:
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line_status = ns16550_inbyte(dev_cfg, LSR(dev)) & LSR_EOB_MASK;
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ns16550_line_status(dev, line_status, read_transfer);
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break;
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case IIR_CH:
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case IIR_RBRF:
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ns16550_read_transfer(dev, read_transfer);
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break;
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case IIR_THRE:
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ns16550_write_transfer(dev, write_transfer);
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break;
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default:
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/* Unhandled interrupt occurred,disable uart interrupts.
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* and report error.
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*/
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if (read_transfer && read_transfer->callback) {
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ns16550_outbyte(dev_cfg, IER(dev), ns16550_inbyte(dev_cfg, IER(dev)) &
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~(IER_RXRDY | IER_LSR));
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read_transfer->callback(read_transfer->callback_data,
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UART_DRIVER_ERROR,
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UART_TRANSFER_FAILED, 0);
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read_transfer->callback = NULL;
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}
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if (write_transfer && write_transfer->callback) {
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ns16550_outbyte(dev_cfg, IER(dev),
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ns16550_inbyte(dev_cfg, IER(dev)) & (~IER_TBE));
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write_transfer->callback(write_transfer->callback_data,
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UART_DRIVER_ERROR,
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UART_TRANSFER_FAILED, 0);
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write_transfer->callback = NULL;
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}
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}
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}
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#endif /* CONFIG_UART_ASYNC_API */
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/**
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* @brief Interrupt service routine.
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*
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@ -1006,6 +1298,10 @@ static void uart_ns16550_isr(const struct device *dev)
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if (dev_data->cb) {
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dev_data->cb(dev, dev_data->cb_data);
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#ifdef CONFIG_UART_ASYNC_API
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} else {
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uart_ns16550_callback(dev);
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#endif
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}
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#ifdef CONFIG_UART_NS16550_WA_ISR_REENABLE_INTERRUPT
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@ -1109,6 +1405,247 @@ static int uart_ns16550_drv_cmd(const struct device *dev, uint32_t cmd,
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#endif /* CONFIG_UART_NS16550_DRV_CMD */
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#ifdef CONFIG_UART_ASYNC_API
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static uint32_t uart_ns16550_decode_line_err(uint32_t line_err)
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{
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uint32_t zephyr_line_err = 0;
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if (line_err & LSR_OE) {
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zephyr_line_err = UART_ERROR_OVERRUN;
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}
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if (line_err & LSR_PE) {
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zephyr_line_err = UART_ERROR_PARITY;
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}
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if (line_err & LSR_FE) {
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zephyr_line_err = UART_ERROR_FRAMING;
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}
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if (line_err & LSR_BI) {
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zephyr_line_err = UART_BREAK;
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}
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return zephyr_line_err;
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}
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static void uart_ns16550_irq_tx_common_cb(void *data, int err, uint32_t status,
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uint32_t len)
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{
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const struct device *dev = data;
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struct uart_ns16550_dev_data *dev_data = dev->data;
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if (dev_data->async_cb) {
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dev_data->async_user_data = (void *)(uintptr_t)
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uart_ns16550_decode_line_err(status);
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dev_data->async_cb(dev, &dev_data->evt, dev_data->async_user_data);
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}
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k_sem_give(GET_TX_SEM(dev));
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}
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static void uart_ns16550_irq_rx_common_cb(void *data, int err, uint32_t status,
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uint32_t len)
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{
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const struct device *dev = data;
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struct uart_ns16550_dev_data *dev_data = dev->data;
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if (dev_data->async_cb) {
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dev_data->async_user_data = (void *)(uintptr_t)
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uart_ns16550_decode_line_err(status);
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dev_data->async_cb(dev, &dev_data->evt, dev_data->async_user_data);
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}
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k_sem_give(GET_RX_SEM(dev));
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}
|
||||
|
||||
static int uart_ns16550_async_callback_set(const struct device *dev,
|
||||
uart_callback_t cb,
|
||||
void *user_data)
|
||||
{
|
||||
struct uart_ns16550_dev_data *dev_data = dev->data;
|
||||
k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
|
||||
|
||||
dev_data->async_cb = cb;
|
||||
dev_data->async_user_data = user_data;
|
||||
|
||||
k_spin_unlock(&dev_data->lock, key);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int uart_ns16550_write_buffer_async(const struct device *dev,
|
||||
const uint8_t *tx_buf,
|
||||
size_t tx_buf_size, int32_t timeout)
|
||||
{
|
||||
struct uart_ns16550_dev_data *dev_data = dev->data;
|
||||
const struct uart_ns16550_device_config * const dev_cfg = dev->config;
|
||||
int ret;
|
||||
|
||||
__ASSERT(tx_buf != NULL, "");
|
||||
__ASSERT(tx_buf_size != 0, "");
|
||||
|
||||
|
||||
k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
|
||||
|
||||
if (k_sem_take(GET_TX_SEM(dev), K_NO_WAIT)) {
|
||||
ret = -EBUSY;
|
||||
goto out;
|
||||
}
|
||||
if (dev_data->async_cb) {
|
||||
dev_data->evt.type = UART_TX_DONE;
|
||||
}
|
||||
|
||||
dev_data->tx_transfer->data = (uint8_t *)tx_buf;
|
||||
dev_data->tx_transfer->data_len = tx_buf_size;
|
||||
dev_data->tx_transfer->callback = uart_ns16550_irq_tx_common_cb;
|
||||
dev_data->tx_transfer->callback_data = (void *)dev;
|
||||
|
||||
dev_data->write_pos = 0;
|
||||
|
||||
/* Set threshold. */
|
||||
ns16550_outbyte(dev_cfg, FCR(dev), (FCR_FIFO | FCR_FIFO_8));
|
||||
|
||||
/* Enable TX holding reg empty interrupt. */
|
||||
ns16550_outbyte(dev_cfg, IER(dev), (ns16550_inbyte(dev_cfg, IER(dev)) | IER_TBE));
|
||||
ret = 0;
|
||||
out:
|
||||
k_spin_unlock(&dev_data->lock, key);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int uart_ns16550_write_abort_async(const struct device *dev)
|
||||
{
|
||||
struct uart_ns16550_dev_data *dev_data = dev->data;
|
||||
const struct uart_ns16550_device_config * const dev_cfg = dev->config;
|
||||
struct uart_ns16550_transfer_t *transfer = dev_data->tx_transfer;
|
||||
int ret;
|
||||
|
||||
k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
|
||||
|
||||
if (dev_data->async_cb) {
|
||||
dev_data->evt.type = UART_TX_ABORTED;
|
||||
}
|
||||
/* No ongoing write transaction to be terminated. */
|
||||
if (transfer == NULL) {
|
||||
ret = -EIO;
|
||||
goto out;
|
||||
}
|
||||
/* Disable TX holding reg empty interrupt. */
|
||||
ns16550_outbyte(dev_cfg, IER(dev), ns16550_inbyte(dev_cfg, IER(dev)) & (~IER_TBE));
|
||||
|
||||
if (transfer) {
|
||||
if (transfer->callback) {
|
||||
transfer->callback(transfer->callback_data,
|
||||
UART_ERROR_CANCELED,
|
||||
UART_TRANSFER_FAILED,
|
||||
dev_data->write_pos);
|
||||
}
|
||||
dev_data->tx_transfer->callback = NULL;
|
||||
dev_data->write_pos = 0;
|
||||
}
|
||||
ret = 0;
|
||||
out:
|
||||
k_spin_unlock(&dev_data->lock, key);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int uart_ns16550_read_buffer_async(const struct device *dev,
|
||||
uint8_t *rx_buf,
|
||||
size_t rx_buf_size,
|
||||
int32_t timeout)
|
||||
{
|
||||
__ASSERT(rx_buf != NULL, "");
|
||||
__ASSERT(rx_buf_size != 0, "");
|
||||
struct uart_ns16550_dev_data *dev_data = dev->data;
|
||||
const struct uart_ns16550_device_config * const dev_cfg = dev->config;
|
||||
int ret;
|
||||
|
||||
k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
|
||||
|
||||
if (k_sem_take(GET_RX_SEM(dev), K_NO_WAIT)) {
|
||||
ret = -EBUSY;
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (dev_data->async_cb) {
|
||||
dev_data->evt.type = UART_RX_RDY;
|
||||
}
|
||||
|
||||
dev_data->rx_transfer->data = rx_buf;
|
||||
dev_data->rx_transfer->data_len = rx_buf_size;
|
||||
dev_data->rx_transfer->callback = uart_ns16550_irq_rx_common_cb;
|
||||
dev_data->rx_transfer->callback_data = (void *)dev;
|
||||
|
||||
dev_data->read_pos = 0;
|
||||
|
||||
/* Set threshold. */
|
||||
ns16550_outbyte(dev_cfg, FCR(dev), (FCR_FIFO | FCR_FIFO_8));
|
||||
|
||||
/*
|
||||
* Enable both 'Receiver Data Available' and 'Receiver
|
||||
* Line Status' interrupts.
|
||||
*/
|
||||
ns16550_outbyte(dev_cfg, IER(dev),
|
||||
(ns16550_inbyte(dev_cfg, IER(dev)) | IER_RXRDY | IER_LSR));
|
||||
ret = 0;
|
||||
out:
|
||||
k_spin_unlock(&dev_data->lock, key);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int uart_ns16550_read_disable_async(const struct device *dev)
|
||||
{
|
||||
struct uart_ns16550_dev_data *dev_data = dev->data;
|
||||
const struct uart_ns16550_device_config * const dev_cfg = dev->config;
|
||||
struct uart_ns16550_transfer_t *transfer = dev_data->rx_transfer;
|
||||
int ret;
|
||||
|
||||
k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
|
||||
|
||||
if (dev_data->async_cb) {
|
||||
dev_data->evt.type = UART_RX_DISABLED;
|
||||
}
|
||||
|
||||
/* No ongoing read transaction to be terminated. */
|
||||
if (transfer == NULL) {
|
||||
ret = -EIO;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/*
|
||||
* Disable both 'Receiver Data Available' and 'Receiver Line Status'
|
||||
* interrupts.
|
||||
*/
|
||||
ns16550_outbyte(dev_cfg, IER(dev),
|
||||
ns16550_inbyte(dev_cfg, IER(dev)) & ~(IER_RXRDY | IER_LSR));
|
||||
|
||||
if (transfer) {
|
||||
if (transfer->callback) {
|
||||
transfer->callback(transfer->callback_data,
|
||||
UART_ERROR_CANCELED,
|
||||
UART_TRANSFER_FAILED,
|
||||
dev_data->read_pos);
|
||||
transfer->callback = NULL;
|
||||
}
|
||||
dev_data->read_pos = 0;
|
||||
}
|
||||
ret = 0;
|
||||
|
||||
out:
|
||||
k_spin_unlock(&dev_data->lock, key);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int uart_ns16550_read_buf_rsp(const struct device *dev, uint8_t *buf,
|
||||
size_t len)
|
||||
{
|
||||
ARG_UNUSED(dev);
|
||||
ARG_UNUSED(buf);
|
||||
ARG_UNUSED(len);
|
||||
|
||||
return -ENOTSUP;
|
||||
}
|
||||
#endif /* CONFIG_UART_ASYNC_API */
|
||||
|
||||
static const struct uart_driver_api uart_ns16550_driver_api = {
|
||||
.poll_in = uart_ns16550_poll_in,
|
||||
|
|
@ -1137,6 +1674,15 @@ static const struct uart_driver_api uart_ns16550_driver_api = {
|
|||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_UART_ASYNC_API
|
||||
.callback_set = uart_ns16550_async_callback_set,
|
||||
.tx = uart_ns16550_write_buffer_async,
|
||||
.tx_abort = uart_ns16550_write_abort_async,
|
||||
.rx_enable = uart_ns16550_read_buffer_async,
|
||||
.rx_disable = uart_ns16550_read_disable_async,
|
||||
.rx_buf_rsp = uart_ns16550_read_buf_rsp,
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_UART_NS16550_LINE_CTRL
|
||||
.line_ctrl_set = uart_ns16550_line_ctrl_set,
|
||||
#endif
|
||||
|
|
@ -1258,10 +1804,36 @@ static const struct uart_driver_api uart_ns16550_driver_api = {
|
|||
|
||||
#define NS16550_BOOT_PRIO(n) \
|
||||
_CONCAT(DEV_BOOT_PRIO, DT_INST_ON_BUS(n, pcie))(n)
|
||||
#ifdef CONFIG_UART_ASYNC_API
|
||||
#define DEV_ASYNC_DECLARE(n) \
|
||||
static K_SEM_DEFINE(uart_##n##_tx_sem, 1, 1); \
|
||||
static K_SEM_DEFINE(uart_##n##_rx_sem, 1, 1); \
|
||||
static struct uart_ns16550_transfer_t tx_##n; \
|
||||
static struct uart_ns16550_transfer_t rx_##n;
|
||||
#else
|
||||
#define DEV_ASYNC_DECLARE(n)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_UART_ASYNC_API
|
||||
#define DEV_CONFIG_ASYNC_INIT(n) \
|
||||
.tx_sem = &uart_##n##_tx_sem, \
|
||||
.rx_sem = &uart_##n##_rx_sem,
|
||||
#else
|
||||
#define DEV_CONFIG_ASYNC_INIT(n)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_UART_ASYNC_API
|
||||
#define DEV_DATA_ASYNC_INIT(n) \
|
||||
.tx_transfer = &tx_##n, \
|
||||
.rx_transfer = &rx_##n,
|
||||
#else
|
||||
#define DEV_DATA_ASYNC_INIT(n)
|
||||
#endif
|
||||
|
||||
#define UART_NS16550_DEVICE_INIT(n) \
|
||||
UART_NS16550_IRQ_FUNC_DECLARE(n); \
|
||||
DEV_PCIE_DECLARE(n); \
|
||||
DEV_ASYNC_DECLARE(n); \
|
||||
IF_ENABLED(DT_INST_NODE_HAS_PROP(n, pinctrl_0), \
|
||||
(PINCTRL_DT_INST_DEFINE(n))); \
|
||||
static const struct uart_ns16550_device_config uart_ns16550_dev_cfg_##n = { \
|
||||
|
|
@ -1280,6 +1852,7 @@ static const struct uart_driver_api uart_ns16550_driver_api = {
|
|||
DEV_CONFIG_IRQ_FUNC_INIT(n) \
|
||||
DEV_CONFIG_PCP_INIT(n) \
|
||||
.reg_interval = (1 << DT_INST_PROP(n, reg_shift)), \
|
||||
DEV_CONFIG_ASYNC_INIT(n) \
|
||||
DEV_CONFIG_PCIE_INIT(n) \
|
||||
IF_ENABLED(DT_INST_NODE_HAS_PROP(n, pinctrl_0), \
|
||||
(.pincfg = PINCTRL_DT_DEV_CONFIG_GET(DT_DRV_INST(n)),)) \
|
||||
|
|
@ -1291,6 +1864,7 @@ static const struct uart_driver_api uart_ns16550_driver_api = {
|
|||
.uart_config.data_bits = UART_CFG_DATA_BITS_8, \
|
||||
.uart_config.flow_ctrl = DEV_DATA_FLOW_CTRL(n), \
|
||||
DEV_DATA_DLF_INIT(n) \
|
||||
DEV_DATA_ASYNC_INIT(n) \
|
||||
}; \
|
||||
DEVICE_DT_INST_DEFINE(n, &uart_ns16550_init, NULL, \
|
||||
&uart_ns16550_dev_data_##n, &uart_ns16550_dev_cfg_##n, \
|
||||
|
|
|
|||
Loading…
Reference in a new issue