drivers: ipm/spi/intc: remove Intel S1000 support

Remove intel_s1000_crb support. The board is no longer available or
supported in the zephyr tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2022-06-13 14:29:20 -04:00
parent 6bd11d0738
commit 2d87948818
4 changed files with 2 additions and 15 deletions

View file

@ -11,9 +11,7 @@
#include "intc_cavs.h"
#if defined(CONFIG_SMP) && (CONFIG_MP_NUM_CPUS > 1)
#if defined(CONFIG_SOC_INTEL_S1000)
#define PER_CPU_OFFSET(x) (0x40 * x)
#elif defined(CONFIG_SOC_SERIES_INTEL_CAVS_V15)
#if defined(CONFIG_SOC_SERIES_INTEL_CAVS_V15)
#define PER_CPU_OFFSET(x) (0x40 * x)
#elif defined(CONFIG_SOC_SERIES_INTEL_CAVS_V18)
#define PER_CPU_OFFSET(x) (0x40 * x)

View file

@ -13,11 +13,6 @@
#include <zephyr/arch/common/sys_io.h>
#include <soc.h>
#ifdef CONFIG_SOC_INTEL_S1000
#include <soc/shim.h>
#endif
#include "ipm_cavs_idc.h"
#ifdef CONFIG_SCHED_IPI_SUPPORTED

View file

@ -10,7 +10,6 @@
/* Redeclaration of the earlier IDC register API for platforms being
* held back on this driver.
*/
#ifndef CONFIG_SOC_INTEL_S1000
# ifndef IPC_DSP_BASE
# define IPC_DSP_BASE(core) (DT_REG_ADDR(DT_NODELABEL(idc)) + 0x80 * (core))
# endif
@ -27,7 +26,6 @@
#define IPC_IDCIETC_DONE BIT(30)
#define IPC_IDCCTL 0x50
#define IPC_IDCCTL_IDCTBIE(x) BIT(x)
#endif
#define IPM_CAVS_IDC_ID_MASK \
(CAVS_IDC_TYPE(CAVS_IDC_TYPE_MASK) | \

View file

@ -97,11 +97,7 @@ struct spi_dw_data {
#define DW_SPI_CTRLR0_SLV_OE_BIT (10)
#define DW_SPI_CTRLR0_SLV_OE BIT(DW_SPI_CTRLR0_SLV_OE_BIT)
#ifdef CONFIG_SOC_INTEL_S1000
#define DW_SPI_CTRLR0_TMOD_SHIFT (10)
#else
#define DW_SPI_CTRLR0_TMOD_SHIFT (8)
#endif
#define DW_SPI_CTRLR0_TMOD_TX_RX (0)
#define DW_SPI_CTRLR0_TMOD_TX (1 << DW_SPI_CTRLR0_TMOD_SHIFT)
@ -112,7 +108,7 @@ struct spi_dw_data {
#define DW_SPI_CTRLR0_DFS_16(__bpw) ((__bpw) - 1)
#define DW_SPI_CTRLR0_DFS_32(__bpw) (((__bpw) - 1) << 16)
#if defined(CONFIG_ARC) || defined(CONFIG_SOC_INTEL_S1000)
#if defined(CONFIG_ARC)
#define DW_SPI_CTRLR0_DFS DW_SPI_CTRLR0_DFS_16
#else
#define DW_SPI_CTRLR0_DFS DW_SPI_CTRLR0_DFS_32