diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 524ce57041..cf19b29e56 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -102,6 +102,13 @@ config RISCV_SOC_INTERRUPT_INIT
 	  Enable SOC-based interrupt initialization
 	  (call soc_interrupt_init, within _IntLibInit when enabled)
 
+config RISCV_SOC_MCAUSE_EXCEPTION_MASK
+	hex
+	default 0x7FFFFFFFFFFFFFFF if 64BIT
+	default 0x7FFFFFFF
+	help
+	  Specify the bits to use for exception code in mcause register.
+
 config RISCV_GENERIC_TOOLCHAIN
 	bool "Compile using generic riscv32 toolchain"
 	default y
diff --git a/soc/riscv/riscv-privilege/common/soc_common.h b/soc/riscv/riscv-privilege/common/soc_common.h
index 37c8d6d7d0..6d3989b847 100644
--- a/soc/riscv/riscv-privilege/common/soc_common.h
+++ b/soc/riscv/riscv-privilege/common/soc_common.h
@@ -25,15 +25,14 @@
 #ifdef CONFIG_64BIT
 /* Interrupt Mask */
 #define SOC_MCAUSE_IRQ_MASK          (1 << 63)
-/* Exception code Mask */
-#define SOC_MCAUSE_EXP_MASK          0x7FFFFFFFFFFFFFFF
 #else
 /* Interrupt Mask */
 #define SOC_MCAUSE_IRQ_MASK          (1 << 31)
-/* Exception code Mask */
-#define SOC_MCAUSE_EXP_MASK          0x7FFFFFFF
 #endif
 
+/* Exception code Mask */
+#define SOC_MCAUSE_EXP_MASK          CONFIG_RISCV_SOC_MCAUSE_EXCEPTION_MASK
+
 /* SOC-Specific EXIT ISR command */
 #define SOC_ERET                     mret