diff --git a/dts/bindings/retained_mem/zephyr,retained-ram.yaml b/dts/bindings/retained_mem/zephyr,retained-ram.yaml
index 5f2c1df124..0b11fdd1bf 100644
--- a/dts/bindings/retained_mem/zephyr,retained-ram.yaml
+++ b/dts/bindings/retained_mem/zephyr,retained-ram.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2023 Nordic Semiconductor ASA
 # SPDX-License-Identifier: Apache-2.0
 
-description: Unitialised RAM-based retained memory area.
+description: Uninitialised RAM-based retained memory area.
 
 compatible: "zephyr,retained-ram"
 
diff --git a/dts/bindings/rng/st,stm32-rng.yaml b/dts/bindings/rng/st,stm32-rng.yaml
index a58a8a81ae..58d4aea8f8 100644
--- a/dts/bindings/rng/st,stm32-rng.yaml
+++ b/dts/bindings/rng/st,stm32-rng.yaml
@@ -18,7 +18,7 @@ properties:
          the clock domain used, for instance:
                    <&rcc STM32_SRC_MSI CLK48_SEL(3)> /* RNG clock domain set to MSI */
          A correctly configured domain clock is required to allow the integrated low
-         sampling clock detection mecanism to behave properly.
+         sampling clock detection mechanism to behave properly.
          In provided example, MSI should be configured to provide 48Mhz clock.
 
   nist-config:
diff --git a/dts/bindings/serial/infineon,xmc4xxx-uart.yaml b/dts/bindings/serial/infineon,xmc4xxx-uart.yaml
index c93ee94082..788ea54c95 100644
--- a/dts/bindings/serial/infineon,xmc4xxx-uart.yaml
+++ b/dts/bindings/serial/infineon,xmc4xxx-uart.yaml
@@ -100,7 +100,7 @@ properties:
          dma1 can connect to lines [8, 11].
       2. For a given interrupt, calculate the service request (SR) number. Note the following
          simple mapping: in USIC0 interrupt 84->SR0, interrupt 85->SR1, ... etc.
-         In USIC1, intterupt 90->SR0, 91->SR1, etc.
+         In USIC1, interrupt 90->SR0, 91->SR1, etc.
       3. Select request_source from Table "DMA Request Source Selection" in XMC4XXX reference
          manual.
 
diff --git a/dts/bindings/serial/st,stm32-uart-base.yaml b/dts/bindings/serial/st,stm32-uart-base.yaml
index 230c384906..9b4852bbc8 100644
--- a/dts/bindings/serial/st,stm32-uart-base.yaml
+++ b/dts/bindings/serial/st,stm32-uart-base.yaml
@@ -90,9 +90,9 @@ properties:
   fifo-enable:
     type: boolean
     description: |
-      Enables transmit and receive FIFO using default FIFO confugration (typically threasholds
+      Enables transmit and receive FIFO using default FIFO configuration (typically thresholds
       set to 1/8).
       In TX, FIFO allows to work in burst mode, easing scheduling of loaded applications. It also
       allows more reliable communication with UART devices sensitive to variation of inter-frames
       delays.
-      In RX, FIFO reduces overrun occurences.
+      In RX, FIFO reduces overrun occurrences.
diff --git a/dts/bindings/spi/infineon,xmc4xxx-spi.yaml b/dts/bindings/spi/infineon,xmc4xxx-spi.yaml
index b3475924e1..a4f30d9940 100644
--- a/dts/bindings/spi/infineon,xmc4xxx-spi.yaml
+++ b/dts/bindings/spi/infineon,xmc4xxx-spi.yaml
@@ -55,7 +55,7 @@ properties:
          dma1 can connect to lines [8, 11].
       2. For a given interrupt, calculate the service request (SR) number. Note the following
          simple mapping: in USIC0 interrupt 84->SR0, interrupt 85->SR1, ... etc.
-         In USIC1, intterupt 90->SR0, 91->SR1, etc.
+         In USIC1, interrupt 90->SR0, 91->SR1, etc.
       3. Select request_source from Table "DMA Request Source Selection" in XMC4XXX reference
          manual.
 
diff --git a/dts/bindings/spi/microchip,xec-qmspi-ldma.yaml b/dts/bindings/spi/microchip,xec-qmspi-ldma.yaml
index 7654612229..418d874bb3 100644
--- a/dts/bindings/spi/microchip,xec-qmspi-ldma.yaml
+++ b/dts/bindings/spi/microchip,xec-qmspi-ldma.yaml
@@ -55,14 +55,14 @@ properties:
     type: int
     description: |
       Delay in QMSPI main clocks from CS# assertion to first clock edge.
-      If not present use hardware default value. Refer to chip documention
+      If not present use hardware default value. Refer to chip documentation
       for QMSPI input clock frequency.
 
   dckcsoff:
     type: int
     description: |
       Delay in QMSPI main clocks from last clock edge to CS# de-assertion.
-      If not present use hardware default value. Refer to chip documention
+      If not present use hardware default value. Refer to chip documentation
       for QMSPI input clock frequency.
 
   dldh:
@@ -76,7 +76,7 @@ properties:
     type: int
     description: |
       Delay in QMSPI main clocks from CS# de-assertion to CS# assertion.
-      If not present use hardware default value. Refer to chip documention
+      If not present use hardware default value. Refer to chip documentation
       for QMSPI input clock frequency.
 
   cs1-freq: