Kconfig: Introduce RISCV_HAS_CLIC

Introduce a new RISCV_HAS_CLIC symbol for platforms using CLIC,
reorganize the Kconfigs and make the Nuclei ECLIC depending on the new
symbol.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>

drivers/interrupt_controller/Kconfig

@@ -16,20 +16,10 @@ config ARCV2_INTERRUPT_UNIT
 	  building a processor, you can configure the processor to include an
 	  interrupt unit. The ARCv2 interrupt unit is highly programmable.
 
-config PLIC
-	bool "Platform Level Interrupt Controller (PLIC)"
-	default y
-	depends on RISCV_HAS_PLIC
-	select MULTI_LEVEL_INTERRUPTS
-	select 2ND_LEVEL_INTERRUPTS
-	help
-	  Platform Level Interrupt Controller provides support
-	  for external interrupt lines defined by the RISC-V SoC;
-
 config SWERV_PIC
 	bool "SweRV EH1 Programmable Interrupt Controller (PIC)"
 	help
-	  Programmable Interrupt Controller for the SweRV EH1 RISC-V CPU;
+	  Programmable Interrupt Controller for the SweRV EH1 RISC-V CPU.
 
 config VEXRISCV_LITEX_IRQ
 	bool "VexRiscv LiteX Interrupt controller"
@@ -82,8 +72,10 @@ source "drivers/interrupt_controller/Kconfig.esp32c3"
 
 source "drivers/interrupt_controller/Kconfig.xec"
 
-source "drivers/interrupt_controller/Kconfig.eclic"
+source "drivers/interrupt_controller/Kconfig.clic"
 
 source "drivers/interrupt_controller/Kconfig.gd32_exti"
 
+source "drivers/interrupt_controller/Kconfig.plic"
+
 endmenu

drivers/interrupt_controller/Kconfig.clic

@@ -1,18 +1,11 @@
-# Nuclei ECLIC interrupt-controller configuration
-
 # Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
 
 DT_COMPAT_NUCLEI_ECLIC = nuclei,eclic
 
-config HAS_NUCLEI_ECLIC
-	bool
-	help
-	  Indicate that the platform has ECLIC.
-
 config NUCLEI_ECLIC
 	bool "Enhanced Core Local Interrupt Controller (ECLIC)"
 	default $(dt_compat_enabled,$(DT_COMPAT_NUCLEI_ECLIC))
-	depends on HAS_NUCLEI_ECLIC
+	depends on RISCV_HAS_CLIC
 	help
 	  Interrupt controller for Nuclei SoC core.

drivers/interrupt_controller/Kconfig.plic

@@ -0,0 +1,12 @@
+# Copyright (c) 2022 Carlo Caione <ccaione@baylibre.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config PLIC
+	bool "Platform Level Interrupt Controller (PLIC)"
+	default y
+	depends on RISCV_HAS_PLIC
+	select MULTI_LEVEL_INTERRUPTS
+	select 2ND_LEVEL_INTERRUPTS
+	help
+	  Platform Level Interrupt Controller provides support
+	  for external interrupt lines defined by the RISC-V SoC.

soc/riscv/riscv-privilege/Kconfig

@@ -13,10 +13,16 @@ config SOC_FAMILY
 	depends on SOC_FAMILY_RISCV_PRIVILEGE
 
 config RISCV_HAS_PLIC
-	bool "Does the SOC provide support for a Platform Level Interrupt Controller"
+	bool "Does the SOC provide support for a Platform Level Interrupt Controller (PLIC)"
 	depends on SOC_FAMILY_RISCV_PRIVILEGE
 	help
-	  Does the SOC provide support for a Platform Level Interrupt Controller
+	  Does the SOC provide support for a Platform Level Interrupt Controller (PLIC).
+
+config RISCV_HAS_CLIC
+	bool "Does the SOC provide support for a Core-Local Interrupt Controller (CLIC)"
+	depends on SOC_FAMILY_RISCV_PRIVILEGE
+	help
+	  Does the SOC provide support for a Core-Local Interrupt Controller (CLIC).
 
 config RISCV_MTVEC_VECTORED_MODE
 	bool "Should the SOC use mtvec in vectored mode"

soc/riscv/riscv-privilege/gd32vf103/Kconfig.series

@@ -13,7 +13,7 @@ config SOC_SERIES_GD32VF103
 	select XIP
 	select GD32_HAS_AFIO_PINMUX
 	select HAS_GD32_HAL
-	select HAS_NUCLEI_ECLIC
+	select RISCV_HAS_CLIC
 
 	help
 	  Enable support for GigaDevice GD32VF1 series SoC