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arc: remove obsolete generic_arc

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Change-Id: Ifa1506cd5c8ff6876a8b945507c7d6caf2f3bbc2
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2016-01-08 12:28:35 -05:00
parent 030c004fd3
commit 32c48d1b2d
8 changed files with 0 additions and 423 deletions
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75
arch/arc/soc/generic_arc/Kconfig
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@ -1,75 +0,0 @@
#
# Copyright (c) 2015 Intel Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
if SOC_GENERIC_ARC
config SOC
default generic_arc
config NUM_IRQ_PRIO_LEVELS
# This processor supports only 2 priority levels:
# 0 for Fast Interrupts (FIRQs) and 1 for Regular Interrupts (IRQs).
default 2
config NUM_REGULAR_IRQ_PRIO_LEVELS
# This processor supports only 1 Regular Interrupt priority level (1).
default 1
config NUM_IRQS
# must be > the highest interrupt number used
default 17
menu "Generic BSP Options"
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 32000000
config RAM_START
default 0x4000 if NSIM
default 0xa8000000
config RAM_SIZE
default 16 if NSIM
default 80
endmenu
config KERNEL_INIT_PRIORITY_DEFAULT
default 40
config KERNEL_INIT_PRIORITY_DEVICE
default 50
config UART_CONSOLE_PRIORITY
default 60
config UART_NSIM_PORT_0_BASE_ADDR
default 0x4242
depends on NSIM
if UART_CONSOLE
config UART_CONSOLE_ON_DEV_NAME
default "UART_0"
config UART_CONSOLE_IRQ
default 41
config UART_CONSOLE_IRQ_PRI
default 0
endif
endif

4
arch/arc/soc/generic_arc/Kconfig.soc
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config SOC_GENERIC_ARC
prompt "Generic ARC Support"
bool

3
arch/arc/soc/generic_arc/Makefile
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obj-y = soc.o
obj-$(CONFIG_IRQ_VECTOR_TABLE_BSP) += irq_vector_table.o
obj-$(CONFIG_SW_ISR_TABLE_BSP) += sw_isr_table.o

53
arch/arc/soc/generic_arc/irq_vector_table.c
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@ -1,53 +0,0 @@
/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file
* @brief IRQ part of vector table for generic arc BSP
*
* This file contains the IRQ part of the vector table. It is meant to be used
* for one of two cases:
*
* a) When software-managed ISRs (SW_ISR_TABLE) is enabled, and in that case it
* binds _IsrWrapper() to all the IRQ entries in the vector table.
*
* b) When the BSP is written so that device ISRs are installed directly in the
* vector table, they are enumerated here.
*/
#include <toolchain.h>
#include <sections.h>
extern void _isr_enter(void);
typedef void (*vth)(void); /* Vector Table Handler */
#if defined(CONFIG_SW_ISR_TABLE)
vth __irq_vector_table _irq_vector_table[CONFIG_NUM_IRQS - 16] = {
[0 ...(CONFIG_NUM_IRQS - 17)] = _isr_enter
};
#elif !defined(CONFIG_IRQ_VECTOR_TABLE_CUSTOM)
extern void _SpuriousIRQ(void);
/* placeholders: fill with real ISRs */
vth __irq_vector_table _irq_vector_table[CONFIG_NUM_IRQS - 16] = {
[0 ...(CONFIG_NUM_IRQS - 17)] = _SpuriousIRQ
};
#endif /* CONFIG_SW_ISR_TABLE */

42
arch/arc/soc/generic_arc/linker.cmd
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@ -1,42 +0,0 @@
/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file
* @brief Linker command/script file
*
* This is the linker script for both standard images and XIP images.
*/
/* Flash base address and size */
#define FLASH_START 0x40034000 /* Flash bank 1 */
#define FLASH_SIZE 152K
/*
* SRAM base address and size
*
* Internal SRAM includes the exception vector table at reset, which is at
* the beginning of the region.
*/
#define SRAM_START CONFIG_RAM_START
#define SRAM_SIZE CONFIG_RAM_SIZE
/* Data Closely Coupled Memory (DCCM) base address and size */
#define DCCM_START 0x80000000
#define DCCM_SIZE 8K
#include <arch/arc/v2/linker.cmd>

56
arch/arc/soc/generic_arc/soc.c
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@ -1,56 +0,0 @@
/*
* Copyright (c) 2014-2015 Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file
* @brief System/hardware module for generic arc BSP
*
* This module provides routines to initialize and support board-level hardware
* for the generic arc platform.
*/
#include <nanokernel.h>
#include "soc.h"
#include <init.h>
#include <uart.h>
/* Cannot use microkernel, since only nanokernel is supported */
#if defined(CONFIG_MICROKERNEL)
#error "Microkernel support is not available"
#endif
/**
*
* @brief perform basic hardware initialization
*
* Hardware initialized:
* - interrupt unit
* - serial port and console driver
*
* RETURNS: N/A
*/
static int generic_arc_init(struct device *arg)
{
ARG_UNUSED(arg);
_arc_v2_irq_unit_init();
return 0;
}
DECLARE_DEVICE_INIT_CONFIG(generic_arc_0, "", generic_arc_init, NULL);
SYS_DEFINE_DEVICE(generic_arc_0, NULL, PRIMARY,
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

126
arch/arc/soc/generic_arc/soc.h
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@ -1,126 +0,0 @@
/*
* Copyright (c) 2014-2015 Wind River Systems, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/**
* @file
* @brief Board configuration macros for the generic arc BSP
*
* This header file is used to specify and describe board-level aspects for the
* generic arc BSP.
*/
#ifndef _BOARD__H_
#define _BOARD__H_
#include <misc/util.h>
/* default system clock */
#define SYSCLK_DEFAULT_IOSC_HZ MHZ(32)
/* address bases */
#define PERIPH_ADDR_BASE_ADC 0x80015000 /* ADC */
#define PERIPH_ADDR_BASE_CREG_MST0 0x80018000 /* CREG Master 0 */
#define PERIPH_ADDR_BASE_CREG_SLV0 0x80018080 /* CREG Slave 0 */
#define PERIPH_ADDR_BASE_CREG_SLV1 0x80018180 /* CREG Slave 1 */
#define PERIPH_ADDR_BASE_GPIO0 0x80017800 /* GPIO 0 */
#define PERIPH_ADDR_BASE_GPIO1 0x80017900 /* GPIO 1 */
#define PERIPH_ADDR_BASE_I2C_MST0 0x80012000 /* I2C Master 0 */
#define PERIPH_ADDR_BASE_I2C_MST1 0x80012100 /* I2C Master 1 */
#define PERIPH_ADDR_BASE_SPI_MST0 0x80010000 /* SPI Master 0 */
#define PERIPH_ADDR_BASE_SPI_MST1 0x80010100 /* SPI Master 1 */
/* IRQs */
#define IRQ_TIMER0 16
#define IRQ_TIMER1 17
#define IRQ_I2C0_RX_AVAIL 18
#define IRQ_I2C0_TX_REQ 19
#define IRQ_I2C0_STOP_DET 20
#define IRQ_I2C0_ERR 21
#define IRQ_I2C1_RX_AVAIL 22
#define IRQ_I2C1_TX_REQ 23
#define IRQ_I2C1_STOP_DET 24
#define IRQ_I2C1_ERR 25
#define IRQ_SPI0_ERR_INT 26
#define IRQ_SPI0_RX_AVAIL 27
#define IRQ_SPI0_TX_REQ 28
#define IRQ_SPI1_ERR_INT 29
#define IRQ_SPI1_RX_AVAIL 30
#define IRQ_SPI1_TX_REQ 31
#define IRQ_ADC_IRQ 32
#define IRQ_ADC_ERR 33
#define IRQ_GPIO0_INTR 34
#define IRQ_GPIO1_INTR 35
#define IRQ_I2C_MST0_INTR 36
#define IRQ_I2C_MST1_INTR 37
#define IRQ_SPI_MST0_INTR 38
#define IRQ_SPI_MST1_INTR 39
#define IRQ_SPI_SLV_INTR 40
#define IRQ_UART0_INTR 41
#define IRQ_UART1_INTR 42
#define IRQ_I2S_INTR 43
#define IRQ_GPIO_INTR 44
#define IRQ_PWM_TIMER_INTR 45
#define IRQ_USB_INTR 46
#define IRQ_RTC_INTR 47
#define IRQ_WDOG_INTR 48
#define IRQ_DMA_CHAN0 49
#define IRQ_DMA_CHAN1 50
#define IRQ_DMA_CHAN2 51
#define IRQ_DMA_CHAN3 52
#define IRQ_DMA_CHAN4 53
#define IRQ_DMA_CHAN5 54
#define IRQ_DMA_CHAN6 55
#define IRQ_DMA_CHAN7 56
#define IRQ_MAILBOXES_INTR 57
#define IRQ_COMPARATORS_INTR 58
#define IRQ_SYS_PMU_INTR 59
#define IRQ_DMA_CHANS_ERR 60
#define IRQ_INT_SRAM_CTLR 61
#define IRQ_INT_FLASH0_CTLR 62
#define IRQ_INT_FLASH1_CTLR 63
#define IRQ_ALWAYS_ON_TMR 64
#define IRQ_ADC_PWR 65
#define IRQ_ADC_CALIB 66
#define IRQ_ALWAYS_ON_GPIO 67
#ifndef _ASMLANGUAGE
#include <misc/util.h>
#include <drivers/rand32.h>
/* ARCv2 timer 0 configuration settings for the system clock */
#ifdef CONFIG_NANOKERNEL
#define CONFIG_ARCV2_TIMER0_CLOCK_FREQ 32000000 /* 32MHz reference clock \
*/
#define CONFIG_ARCV2_TIMER1_CLOCK_FREQ CONFIG_ARCV2_TIMER0_CLOCK_FREQ
#endif /* CONFIG_NANOKERNEL */
#define CONFIG_ARCV2_TIMER0_INT_LVL IRQ_TIMER0
#define CONFIG_ARCV2_TIMER0_INT_PRI 0
#define CONFIG_ARCV2_TIMER1_INT_LVL IRQ_TIMER1
#define CONFIG_ARCV2_TIMER1_INT_PRI 1
#endif /* !_ASMLANGUAGE */
#endif /* _BOARD__H_ */

64
arch/arc/soc/generic_arc/sw_isr_table.S
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@ -1,64 +0,0 @@
/* sw_isr_table.S - ISR table for static ISR declarations for ARC */
/*
* Copyright (c) 2015 Intel Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#define _ASMLANGUAGE
#include <toolchain.h>
#include <sections.h>
#include <arch/cpu.h>
/*
* enable preprocessor features, such
* as %expr - evaluate the expression and use it as a string
*/
.altmacro
/*
* Define an ISR table entry
* Define symbol as weak and give the section .gnu.linkonce
* prefix. This allows linker overload the symbol and the
* whole section by the one defined by a device driver
*/
.macro _isr_table_entry_declare index
WDATA(_isr_irq\index)
.section .gnu.linkonce.isr_irq\index
_isr_irq\index: .word 0xABAD1DEA, _irq_spurious
.endm
/*
* Declare the ISR table
*/
.macro _isr_table_declare from, to
counter = \from
.rept (\to - \from)
_isr_table_entry_declare %counter
counter = counter + 1
.endr
.endm
GTEXT(_irq_spurious)
GDATA(_sw_isr_table)
.section .isr_irq16
.align
_sw_isr_table:
/*In ARC architecture, IRQ 0-15 are reserved for the system and are not
assignable by the user, for that reason the isr table linker section
start at IRQ 16*/
_isr_table_declare 16 CONFIG_NUM_IRQS