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clock: stm32f4: Fix range of CLOCK_STM32F4X_PLLN_MULTIPLIER config

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The PLLN multiplier can range between 50 and 432 on all STM32F4, except
on the STM32F401 where the lower bound is restricted to 192.

Fix the range property and the help text to reflect this reality.

Change-Id: I7b93e84b321f7869aaf611287344cd3e25c893c8
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
This commit is contained in:
Florian Vaussard 2017-03-10 15:51:22 +01:00 committed by Kumar Gala
parent 9b6140eafc
commit 33579adef9
1 changed files with 5 additions and 3 deletions
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8
drivers/clock_control/Kconfig.stm32f4x
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@ -84,11 +84,13 @@ config CLOCK_STM32F4X_PLLN_MULTIPLIER
int "Multiplier factor for PLL VCO output clock"
depends on CLOCK_CONTROL_STM32F4X && CLOCK_STM32F4X_SYSCLK_SRC_PLL
default 336
range 192 432
range 192 432 if SOC_STM32F401XE
range 50 432
help
PLLN multiplier factor needs to be set correctly to ensure that the
VCO output frequency is between 192 and 432 MHz.
Allowed values: 192-432
VCO output frequency is between 100 and 432 MHz, except on STM32F401
where the frequency must be between 192 and 432 MHz.
Allowed values: 50-432 (STM32F401: 192-432)
config CLOCK_STM32F4X_PLLP_DIV_FACTOR
int "PLL division factor for main system clock"