soc: xtensa: intel_adsp: fix memory bank shutdown
Amount of memory banks should vary depending on platform, otherwise power down sequence might result in ipc timeout as the memory used by the ipc itself is shutdown. Lift the needed defines from sram.c to adsp_memory.h and shorten the names to avoid collision with sof code. No functional change to sram.c. Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
This commit is contained in:
Jaska Uimonen
Anas Nashif
parent
5dfaf23f47
commit
339b00de11
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@ -6,7 +6,6 @@
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#ifndef ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
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#define ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
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#include <zephyr/devicetree.h>
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#include <adsp-vectors.h>
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@ -22,6 +21,14 @@
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#define RAM_BASE (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE + VECTOR_TBL_SIZE)
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#define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE)
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#define SRAM_BANK_SIZE (64 * 1024)
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#define EBB_SEG_SIZE 32
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#define HPSRAM_EBB_COUNT (DT_REG_SIZE(DT_NODELABEL(sram0)) / SRAM_BANK_SIZE)
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/* div_round_up, but zephyr version is not defined for assembler where this is also used */
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#define HPSRAM_SEGMENTS (HPSRAM_EBB_COUNT + EBB_SEG_SIZE - 1) / EBB_SEG_SIZE
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#define HPSRAM_MEMMASK(idx) ((1ULL << (HPSRAM_EBB_COUNT - EBB_SEG_SIZE * idx)) - 1)
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/* The rimage tool produces two blob addresses we need to find: one is
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* our bootloader code block which starts at its entry point, the
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* other is the "manifest" containing the HP-SRAM data to unpack,
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@ -15,6 +15,7 @@
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#include <zephyr/cache.h>
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#include <cpu_init.h>
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#include <adsp_memory.h>
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#include <adsp_shim.h>
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#include <adsp_clk.h>
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#include <cavs-idc.h>
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@ -36,7 +37,6 @@ LOG_MODULE_REGISTER(soc);
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#ifdef CONFIG_PM_POLICY_CUSTOM
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#define SRAM_ALIAS_BASE 0x9E000000
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#define SRAM_ALIAS_MASK 0xFF000000
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#define EBB_BANKS_IN_SEGMENT 32
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#define SRAM_ALIAS_OFFSET 0x20000000
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#define L2_INTERRUPT_NUMBER 4
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@ -81,11 +81,12 @@ __weak void pm_state_set(enum pm_state state, uint8_t substate_id)
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soc_cpus_active[cpu] = false;
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sys_cache_data_flush_and_invd_all();
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if (cpu == 0) {
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uint32_t ebb = EBB_BANKS_IN_SEGMENT;
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uint32_t hpsram_mask[HPSRAM_SEGMENTS];
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/* turn off all HPSRAM banks - get a full bitmap */
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uint32_t hpsram_mask = (1 << ebb) - 1;
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for (int i = 0; i < HPSRAM_SEGMENTS; i++)
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hpsram_mask[i] = HPSRAM_MEMMASK(i);
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/* do power down - this function won't return */
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power_down_cavs(true, uncache_to_cache(&hpsram_mask));
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power_down_cavs(true, uncache_to_cache(&hpsram_mask[0]));
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} else {
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z_xt_ints_on(core_desc[cpu].intenable);
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k_cpu_idle();
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@ -4,6 +4,7 @@
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#include "asm_ldo_management.h"
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#include "asm_memory_management.h"
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#include "adsp_memory.h"
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#define IPC_HOST_BASE 0x00071E00
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#define IPC_DIPCIDD 0x18
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@ -42,8 +43,6 @@ sram_dis_loop_cnt:
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#define host_base a10
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#define pfl_reg a15
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#define MAX_MEMORY_SEGMENTS 2
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power_down_cavs:
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entry sp, 32
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/**
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@ -102,8 +101,8 @@ _PD_DISABLE_HPSRAM:
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* where mask is given in pu32_hpsram_mask register
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*/
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.set seg_index, MAX_MEMORY_SEGMENTS - 1
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.rept MAX_MEMORY_SEGMENTS
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.set seg_index, HPSRAM_SEGMENTS - 1
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.rept HPSRAM_SEGMENTS
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l32i temp_reg0, pu32_hpsram_mask, 4 * seg_index
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m_cavs_hpsram_power_change\
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/*segment_index=*/ seg_index,\
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@ -13,15 +13,11 @@
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#include <cpu_init.h>
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#include "manifest.h"
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#define DELAY_COUNT 256
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#define LPSRAM_MASK(x) 0x00000003
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#define SRAM_BANK_SIZE (64 * 1024)
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#define EBB_SEGMENT_SIZE 32
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#define PLATFORM_INIT_HPSRAM
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#define PLATFORM_INIT_LPSRAM
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#define PLATFORM_HPSRAM_EBB_COUNT (DT_REG_SIZE(DT_NODELABEL(sram0)) / SRAM_BANK_SIZE)
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BUILD_ASSERT((DT_REG_SIZE(DT_NODELABEL(sram0)) % SRAM_BANK_SIZE) == 0,
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"sram0 must be divisible by 64*1024 bank size.");
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@ -33,7 +29,7 @@ static __imr void hp_sram_pm_banks(uint32_t banks)
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{
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#ifdef CONFIG_ADSP_INIT_HPSRAM
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uint32_t status, ebb_mask0, ebb_mask1, ebb_avail_mask0, ebb_avail_mask1,
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total_banks_count = PLATFORM_HPSRAM_EBB_COUNT;
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total_banks_count = HPSRAM_EBB_COUNT;
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CAVS_SHIM.ldoctl = SHIM_LDOCTL_HPSRAM_LDO_ON;
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@ -44,19 +40,19 @@ static __imr void hp_sram_pm_banks(uint32_t banks)
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* bit masks reflect total number of available EBB (banks) in each
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* segment; current implementation supports 2 segments 0,1
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*/
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if (total_banks_count > EBB_SEGMENT_SIZE) {
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ebb_avail_mask0 = (uint32_t)GENMASK(EBB_SEGMENT_SIZE - 1, 0);
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if (total_banks_count > EBB_SEG_SIZE) {
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ebb_avail_mask0 = (uint32_t)GENMASK(EBB_SEG_SIZE - 1, 0);
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ebb_avail_mask1 = (uint32_t)GENMASK(total_banks_count -
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EBB_SEGMENT_SIZE - 1, 0);
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EBB_SEG_SIZE - 1, 0);
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} else {
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ebb_avail_mask0 = (uint32_t)GENMASK(total_banks_count - 1, 0);
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ebb_avail_mask1 = 0;
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}
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/* bit masks of banks that have to be powered up in each segment */
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if (banks > EBB_SEGMENT_SIZE) {
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ebb_mask0 = (uint32_t)GENMASK(EBB_SEGMENT_SIZE - 1, 0);
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ebb_mask1 = (uint32_t)GENMASK(banks - EBB_SEGMENT_SIZE - 1,
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if (banks > EBB_SEG_SIZE) {
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ebb_mask0 = (uint32_t)GENMASK(EBB_SEG_SIZE - 1, 0);
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ebb_mask1 = (uint32_t)GENMASK(banks - EBB_SEG_SIZE - 1,
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0);
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} else {
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/* assumption that ebb_in_use is > 0 */
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