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drivers/spi: stm32u5 spi support

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Add the specific driver functions for the SPI
of the stm32u5 device.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
Francois Ramu 2021-10-01 17:44:25 +02:00 committed by Christopher Friedt
parent 71bde8a858
commit 33e0f1a87a
2 changed files with 32 additions and 16 deletions
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12
drivers/spi/spi_ll_stm32.c
View file

@ -39,7 +39,8 @@ LOG_MODULE_REGISTER(spi_ll_stm32);
* for F1 family defines an unused LL_SPI_SR_FRE.
*/
#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
defined(CONFIG_SOC_SERIES_STM32H7X)
defined(CONFIG_SOC_SERIES_STM32H7X) || \
defined(CONFIG_SOC_SERIES_STM32U5X)
#define SPI_STM32_ERR_MSK (LL_SPI_SR_UDR | LL_SPI_SR_CRCE | LL_SPI_SR_MODF | \
LL_SPI_SR_OVR | LL_SPI_SR_TIFRE)
#else
@ -265,8 +266,10 @@ static void spi_stm32_shift_m(SPI_TypeDef *spi, struct spi_stm32_data *data)
}
#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
defined(CONFIG_SOC_SERIES_STM32H7X)
/* With the STM32MP1 and the STM32H7, if the device is the SPI master,
defined(CONFIG_SOC_SERIES_STM32H7X) || \
defined(CONFIG_SOC_SERIES_STM32U5X)
/* With the STM32MP1, STM32U5 and the STM32H7,
* if the device is the SPI master,
* we need to enable the start of the transfer with
* LL_SPI_StartMasterTransfer(spi)
*/
@ -526,7 +529,8 @@ static int spi_stm32_configure(const struct device *dev,
if (config->cs || !IS_ENABLED(CONFIG_SPI_STM32_USE_HW_SS)) {
#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
defined(CONFIG_SOC_SERIES_STM32H7X)
defined(CONFIG_SOC_SERIES_STM32H7X) || \
defined(CONFIG_SOC_SERIES_STM32U5X)
if (SPI_OP_MODE_GET(config->operation) == SPI_OP_MODE_MASTER) {
if (LL_SPI_GetNSSPolarity(spi) == LL_SPI_NSS_POLARITY_LOW)
LL_SPI_SetInternalSSLevel(spi, LL_SPI_SS_LEVEL_HIGH);

36
drivers/spi/spi_ll_stm32.h
View file

@ -57,7 +57,8 @@ struct spi_stm32_data {
static inline uint32_t ll_func_tx_is_empty(SPI_TypeDef *spi)
{
#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
defined(CONFIG_SOC_SERIES_STM32H7X)
defined(CONFIG_SOC_SERIES_STM32H7X) || \
defined(CONFIG_SOC_SERIES_STM32U5X)
return LL_SPI_IsActiveFlag_TXP(spi);
#else
return LL_SPI_IsActiveFlag_TXE(spi);
@ -67,7 +68,8 @@ static inline uint32_t ll_func_tx_is_empty(SPI_TypeDef *spi)
static inline uint32_t ll_func_rx_is_not_empty(SPI_TypeDef *spi)
{
#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
defined(CONFIG_SOC_SERIES_STM32H7X)
defined(CONFIG_SOC_SERIES_STM32H7X) || \
defined(CONFIG_SOC_SERIES_STM32U5X)
return LL_SPI_IsActiveFlag_RXP(spi);
#else
return LL_SPI_IsActiveFlag_RXNE(spi);
@ -77,7 +79,8 @@ static inline uint32_t ll_func_rx_is_not_empty(SPI_TypeDef *spi)
static inline void ll_func_enable_int_tx_empty(SPI_TypeDef *spi)
{
#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
defined(CONFIG_SOC_SERIES_STM32H7X)
defined(CONFIG_SOC_SERIES_STM32H7X) || \
defined(CONFIG_SOC_SERIES_STM32U5X)
LL_SPI_EnableIT_TXP(spi);
#else
LL_SPI_EnableIT_TXE(spi);
@ -87,7 +90,8 @@ static inline void ll_func_enable_int_tx_empty(SPI_TypeDef *spi)
static inline void ll_func_enable_int_rx_not_empty(SPI_TypeDef *spi)
{
#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
defined(CONFIG_SOC_SERIES_STM32H7X)
defined(CONFIG_SOC_SERIES_STM32H7X) || \
defined(CONFIG_SOC_SERIES_STM32U5X)
LL_SPI_EnableIT_RXP(spi);
#else
LL_SPI_EnableIT_RXNE(spi);
@ -97,7 +101,8 @@ static inline void ll_func_enable_int_rx_not_empty(SPI_TypeDef *spi)
static inline void ll_func_enable_int_errors(SPI_TypeDef *spi)
{
#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
defined(CONFIG_SOC_SERIES_STM32H7X)
defined(CONFIG_SOC_SERIES_STM32H7X) || \
defined(CONFIG_SOC_SERIES_STM32U5X)
LL_SPI_EnableIT_UDR(spi);
LL_SPI_EnableIT_OVR(spi);
LL_SPI_EnableIT_CRCERR(spi);
@ -111,7 +116,8 @@ static inline void ll_func_enable_int_errors(SPI_TypeDef *spi)
static inline void ll_func_disable_int_tx_empty(SPI_TypeDef *spi)
{
#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
defined(CONFIG_SOC_SERIES_STM32H7X)
defined(CONFIG_SOC_SERIES_STM32H7X) || \
defined(CONFIG_SOC_SERIES_STM32U5X)
LL_SPI_DisableIT_TXP(spi);
#else
LL_SPI_DisableIT_TXE(spi);
@ -121,7 +127,8 @@ static inline void ll_func_disable_int_tx_empty(SPI_TypeDef *spi)
static inline void ll_func_disable_int_rx_not_empty(SPI_TypeDef *spi)
{
#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
defined(CONFIG_SOC_SERIES_STM32H7X)
defined(CONFIG_SOC_SERIES_STM32H7X) || \
defined(CONFIG_SOC_SERIES_STM32U5X)
LL_SPI_DisableIT_RXP(spi);
#else
LL_SPI_DisableIT_RXNE(spi);
@ -131,7 +138,8 @@ static inline void ll_func_disable_int_rx_not_empty(SPI_TypeDef *spi)
static inline void ll_func_disable_int_errors(SPI_TypeDef *spi)
{
#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
defined(CONFIG_SOC_SERIES_STM32H7X)
defined(CONFIG_SOC_SERIES_STM32H7X) || \
defined(CONFIG_SOC_SERIES_STM32U5X)
LL_SPI_DisableIT_UDR(spi);
LL_SPI_DisableIT_OVR(spi);
LL_SPI_DisableIT_CRCERR(spi);
@ -145,7 +153,8 @@ static inline void ll_func_disable_int_errors(SPI_TypeDef *spi)
static inline uint32_t ll_func_spi_is_busy(SPI_TypeDef *spi)
{
#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
defined(CONFIG_SOC_SERIES_STM32H7X)
defined(CONFIG_SOC_SERIES_STM32H7X) || \
defined(CONFIG_SOC_SERIES_STM32U5X)
return (!LL_SPI_IsActiveFlag_MODF(spi) &&
!LL_SPI_IsActiveFlag_TXC(spi));
#else
@ -160,7 +169,8 @@ static inline uint32_t ll_func_spi_is_busy(SPI_TypeDef *spi)
static inline void ll_func_set_fifo_threshold_8bit(SPI_TypeDef *spi)
{
#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
defined(CONFIG_SOC_SERIES_STM32H7X)
defined(CONFIG_SOC_SERIES_STM32H7X) || \
defined(CONFIG_SOC_SERIES_STM32U5X)
LL_SPI_SetFIFOThreshold(spi, LL_SPI_FIFO_TH_01DATA);
#else
LL_SPI_SetRxFIFOThreshold(spi, LL_SPI_RX_FIFO_TH_QUARTER);
@ -170,7 +180,8 @@ static inline void ll_func_set_fifo_threshold_8bit(SPI_TypeDef *spi)
static inline void ll_func_set_fifo_threshold_16bit(SPI_TypeDef *spi)
{
#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
defined(CONFIG_SOC_SERIES_STM32H7X)
defined(CONFIG_SOC_SERIES_STM32H7X) || \
defined(CONFIG_SOC_SERIES_STM32U5X)
LL_SPI_SetFIFOThreshold(spi, LL_SPI_FIFO_TH_02DATA);
#else
LL_SPI_SetRxFIFOThreshold(spi, LL_SPI_RX_FIFO_TH_HALF);
@ -181,7 +192,8 @@ static inline void ll_func_set_fifo_threshold_16bit(SPI_TypeDef *spi)
static inline void ll_func_disable_spi(SPI_TypeDef *spi)
{
#if defined(CONFIG_SOC_SERIES_STM32MP1X) || \
defined(CONFIG_SOC_SERIES_STM32H7X)
defined(CONFIG_SOC_SERIES_STM32H7X) || \
defined(CONFIG_SOC_SERIES_STM32U5X)
if (LL_SPI_IsActiveMasterTransfer(spi)) {
LL_SPI_SuspendMasterTransfer(spi);
while (LL_SPI_IsActiveMasterTransfer(spi)) {