patrick/zephyr
1
0
Fork 0
Code Issues Pull requests Actions 8 Packages Projects Releases Wiki Activity

boards: nxp: imx8qxp_mek: add pinctrl for SAI1 node

Browse source 
Add pinctrl for SAI1 node. This means:
	1) Adding definitions for the pads used by SAI1.
	2) Creating a pin group and referencing it in the
	SAI1 node via the `pinctrl-0` property.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This commit is contained in:
Laurentiu Mihalcea 2024-03-29 11:49:08 +02:00 committed by Fabio Baltieri
parent f4c73105e5
commit 34410d5366
3 changed files with 38 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

25
boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp-pinctrl.dtsi
View file

@ -14,6 +14,22 @@
iomuxc_uart2_tx_uart2_tx: IOMUXC_UART2_TX_UART2_TX {
pinmux = <SC_P_UART2_TX IMX8QXP_DMA_LPUART2_TX_UART2_TX>;
};
iomuxc_adma_sai1_txfs_sai1_rxfs: IOMUXC_ADMA_SAI1_TXFS_SAI1_RXFS {
pinmux = <SC_P_SAI1_RXFS IMX8QXP_ADMA_SAI1_TXFS_SAI1_RXFS>;
};
iomuxc_adma_sai1_rxd_sai1_rxd: IOMUXC_ADMA_SAI1_RXD_SAI1_RXD {
pinmux = <SC_P_SAI1_RXD IMX8QXP_ADMA_SAI1_RXD_SAI1_RXD>;
};
iomuxc_adma_sai1_txc_sai1_rxc: IOMUXC_ADMA_SAI1_TXC_SAI1_RXC {
pinmux = <SC_P_SAI1_RXC IMX8QXP_ADMA_SAI1_TXC_SAI1_RXC>;
};
iomuxc_adma_sai1_txd_spi0_cs1: IOMUXC_ADMA_SAI1_TXD_SPI0_CS1 {
pinmux = <SC_P_SPI0_CS1 IMX8QXP_ADMA_SAI1_TXD_SPI0_CS1>;
};
};
&pinctrl {
@ -23,4 +39,13 @@
<&iomuxc_uart2_tx_uart2_tx>;
};
};
sai1_default: sai1_default {
group0 {
pinmux = <&iomuxc_adma_sai1_txfs_sai1_rxfs>,
<&iomuxc_adma_sai1_rxd_sai1_rxd>,
<&iomuxc_adma_sai1_txc_sai1_rxc>,
<&iomuxc_adma_sai1_txd_spi0_cs1>;
};
};
};

5
boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts
View file

@ -27,6 +27,11 @@
pinctrl-names = "default";
};
&sai1 {
pinctrl-0 = <&sai1_default>;
pinctrl-names = "default";
};
&irqsteer {
reg = <0x51080000 DT_SIZE_K(64)>;
};

8
include/zephyr/dt-bindings/pinctrl/imx8qxp-pinctrl.h
View file

@ -8,11 +8,19 @@
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IMX8QXP_PINCTRL_H_
/* values for pad field */
#define SC_P_SAI1_RXD 86
#define SC_P_SAI1_RXC 87
#define SC_P_SAI1_RXFS 88
#define SC_P_SPI0_CS1 96
#define SC_P_UART2_TX 113
#define SC_P_UART2_RX 114
/* mux values */
#define IMX8QXP_DMA_LPUART2_RX_UART2_RX 0 /* UART2_RX ---> DMA_LPUART2_RX */
#define IMX8QXP_DMA_LPUART2_TX_UART2_TX 0 /* DMA_LPUART2_TX ---> UART2_TX */
#define IMX8QXP_ADMA_SAI1_TXFS_SAI1_RXFS 1 /* ADMA_SAI1_TXFS <---> SAI1_RXFS */
#define IMX8QXP_ADMA_SAI1_RXD_SAI1_RXD 0 /* ADMA_SAI1_RXD <--- SAI1_RXD */
#define IMX8QXP_ADMA_SAI1_TXC_SAI1_RXC 1 /* ADMA_SAI1_TXC <---> SAI1_RXC */
#define IMX8QXP_ADMA_SAI1_TXD_SPI0_CS1 2 /* ADMA_SAI1_TXD ---> SPI0_CS1 */
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_IMX8QXP_PINCTRL_H_ */