From 34ce476ce6eda664552a2676132d387278133b3c Mon Sep 17 00:00:00 2001
From: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
Date: Sat, 22 Jul 2023 09:51:25 +0300
Subject: [PATCH] soc: smartbond: da1469x: Support Global Foundries silicon

Add support for the GF silicon variant.

Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
---
 soc/arm/renesas_smartbond/da1469x/soc.c | 46 ++++++++++++++++++++++---
 1 file changed, 41 insertions(+), 5 deletions(-)

diff --git a/soc/arm/renesas_smartbond/da1469x/soc.c b/soc/arm/renesas_smartbond/da1469x/soc.c
index 7bef1f9fdf..531bd4b114 100644
--- a/soc/arm/renesas_smartbond/da1469x/soc.c
+++ b/soc/arm/renesas_smartbond/da1469x/soc.c
@@ -8,6 +8,12 @@
 #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/linker/linker-defs.h>
 #include <string.h>
+#include <DA1469xAB.h>
+#include <da1469x_clock.h>
+#include <da1469x_otp.h>
+#include <da1469x_pd.h>
+#include <da1469x_pdc.h>
+#include <da1469x_trimv.h>
 
 #define REMAP_ADR0_QSPI           0x2
 
@@ -107,17 +113,47 @@ void z_arm_platform_init(void)
 #endif
 }
 
-static int renesas_da14699_init(void)
+static int renesas_da1469x_init(void)
 {
 	/* Freeze watchdog until configured */
 	GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_SYS_WDOG_Msk;
+
 	/* Reset clock dividers to 0 */
 	CRG_TOP->CLK_AMBA_REG &= ~(CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk |
-				   CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk);
-	/* Enable all power domains except for radio */
-	CRG_TOP->PMU_CTRL_REG = 0x02;
+				CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk);
+
+	CRG_TOP->PMU_CTRL_REG |= (CRG_TOP_PMU_CTRL_REG_TIM_SLEEP_Msk   |
+				CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Msk  |
+				CRG_TOP_PMU_CTRL_REG_COM_SLEEP_Msk     |
+				CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Msk);
+
+	/* PDC should take care of PD_SYS */
+	CRG_TOP->PMU_CTRL_REG &= ~CRG_TOP_PMU_CTRL_REG_SYS_SLEEP_Msk;
+
+	/*
+	 *	Due to crosstalk issues any power rail can potentially
+	 *	issue a fake event. This is typically observed upon
+	 *	switching power sources, that is DCDC <--> LDOs <--> Retention LDOs.
+	 */
+	CRG_TOP->BOD_CTRL_REG &= ~(CRG_TOP_BOD_CTRL_REG_BOD_V14_EN_Msk |
+				CRG_TOP_BOD_CTRL_REG_BOD_V18F_EN_Msk   |
+				CRG_TOP_BOD_CTRL_REG_BOD_VDD_EN_Msk    |
+				CRG_TOP_BOD_CTRL_REG_BOD_V18P_EN_Msk   |
+				CRG_TOP_BOD_CTRL_REG_BOD_V18_EN_Msk    |
+				CRG_TOP_BOD_CTRL_REG_BOD_V30_EN_Msk    |
+				CRG_TOP_BOD_CTRL_REG_BOD_VBAT_EN_Msk);
+
+	da1469x_pdc_reset();
+
+	da1469x_otp_init();
+	da1469x_trimv_init_from_otp();
+
+	da1469x_pd_init();
+	da1469x_pd_acquire(MCU_PD_DOMAIN_SYS);
+	da1469x_pd_acquire(MCU_PD_DOMAIN_TIM);
+	da1469x_pd_acquire(MCU_PD_DOMAIN_COM);
 
 	return 0;
 }
 
-SYS_INIT(renesas_da14699_init, PRE_KERNEL_1, 0);
+SYS_INIT(renesas_da1469x_init, PRE_KERNEL_1, 0);