samples: drivers: fpga: merge both samples and add sample.yaml

Merge the fpga_controller and fpga_controller shell
sample applications and add sample.yaml to enable testing in
twister.

Fixes #47613

Signed-off-by: Aastha Grover <aastha.grover@intel.com>

samples/drivers/fpga/fpga_controller/README.md

@@ -1,21 +0,0 @@
-# Zephyr FPGA controller
-This module is an FPGA driver that can easily load a bitstream, reset it, check its status, enable or disable the FPGA.
-This sample demonstrates how to use the FPGA driver API.
-Currently the sample works with [Quicklogic Quickfeather board](https://github.com/QuickLogic-Corp/quick-feather-dev-board).
-
-## Requirements
-* Zephyr RTOS
-* [Quicklogic Quickfeather board](https://github.com/QuickLogic-Corp/quick-feather-dev-board)
-
-## Building
-
-For the QuickLogic QuickFeather board:
-```bash
-west build -b quick_feather samples/drivers/fpga/fpga_controller
-```
-
-## Running
-See [QuickFeather programming and debugging](https://docs.zephyrproject.org/latest/boards/arm/quick_feather/doc/index.html#programming-and-debugging) on how to load an image to the board.
-
-## Sample output
-Once the board is programmed, the LED should alternately flash red and green.

samples/drivers/fpga/fpga_controller/README.rst

@@ -0,0 +1,115 @@
+.. _samples_fpga_controller:
+
+Zephyr FPGA controller
+######################
+
+Overview
+********
+This module is an FPGA driver that can easily load a bitstream, reset it, check its status, enable or disable the FPGA.
+This sample demonstrates how to use the FPGA driver API and the the FPGA controller shell subsystem.
+Currently the sample works with [Quicklogic Quickfeather board](https://github.com/QuickLogic-Corp/quick-feather-dev-board).
+
+Requirements
+************
+
+* Zephyr RTOS
+  or
+* Zephyr RTOS with shell subsystem enabled (for shell application)
+* [Quicklogic Quickfeather board](https://github.com/QuickLogic-Corp/quick-feather-dev-board)
+
+Building
+********
+
+For building on QuickLogic QuickFeather board:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/drivers/fpga/fpga_controller
+   :host-os: unix
+   :board: quick_feather
+   :goals: build
+
+
+To build the FPGA Controller shell application, use the supplied
+configuration file prj_shell.conf:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/drivers/fpga/fpga_controller
+   :host-os: unix
+   :board: quick_feather
+   :conf: prj_shell.conf
+   :goals: build
+   :compact:
+
+
+Running
+*******
+
+See [QuickFeather programming and debugging](https://docs.zephyrproject.org/latest/boards/arm/quick_feather/doc/index.html#programming-and-debugging) on how to load an image to the board.
+
+Sample output
+=============
+
+Once the board is programmed, the LED should alternately flash red and green.
+
+For the FPGA controller shell application, after connecting to the shell console you should see the following output:
+
+.. code-block:: console
+
+    Address of the bitstream (red): 0xADDR
+    Address of the bitstream (green): 0xADDR
+    Size of the bitstream (red): 75960
+    Size of the bitstream (green): 75960
+
+    uart:~$
+
+This sample is already prepared with bitstreams.
+After executing the sample, you can see at what address it is stored and its size in bytes.
+
+The FPGA controller command can now be used (``fpga load <device> <address> <size in bytes>``):
+
+.. code-block:: console
+
+    uart:~$ fpga load FPGA 0x2001a46c 75960
+    FPGA: loading bitstream
+
+
+The LED should start blinking (color depending on the selected bitstream).
+To upload the bitstream again you need to reset the FPGA:
+
+.. code-block:: console
+
+    uart:~$ fpga reset FPGA
+    FPGA: resetting FPGA
+
+You can also use your own bitstream.
+To load a bitstream into device memory, use `devmem load` command.
+It is important to use the -e option when sending a bistream via `xxd`:
+
+.. code-block:: console
+
+    uart:~$ devmem load -e 0x10000
+    Loading...
+    Press ctrl-x + ctrl-q to stop
+
+Now, the loader is waiting for data.
+You can either type it directly from the console or send it from the host PC (replace `ttyX` with the appropriate one for your shell console):
+
+.. code-block:: console
+
+    xxd -p data > /dev/ttyX
+
+(It is important to use plain-style hex dump)
+Once the data is transferred, use `ctrl-x + ctrl-q` to quit loader.
+It will print the sum of the read bytes and return to the shell:
+
+.. code-block:: console
+
+    Number of bytes read: 75960
+    uart:~$
+
+Now the bitstream can be uploaded again.
+
+.. code-block:: console
+
+    uart:~$ fpga load FPGA 0x10000 75960
+    FPGA: loading bitstream

samples/drivers/fpga/fpga_controller/sample.yaml

@@ -0,0 +1,13 @@
+sample:
+  name: FPGA Controller sample
+
+common:
+    tags: FPGA
+    build_only: true
+
+tests:
+  sample.drivers.fpga_controller:
+    platform_allow: quick_feather
+  sample.drivers.fpga_controller.shell:
+    platform_allow: quick_feather
+    extra_args: CONF_FILE="prj_shell.conf"

samples/drivers/fpga/fpga_controller/src/main.c

@@ -5,6 +5,7 @@
  */
 
 #include <zephyr/zephyr.h>
+#include <zephyr/shell/shell.h>
 #include <zephyr/device.h>
 #include <zephyr/sys/printk.h>
 #include <zephyr/drivers/fpga.h>
@@ -23,6 +24,12 @@ void main(void)
 			       PAD_SMT_DISABLE | PAD_REN_DISABLE | PAD_SR_SLOW |
 			       PAD_CTRL_SEL_AO_REG); /* Enable green led */
 
+#if CONFIG_SHELL
+	printk("Address of the bitstream (red): %p\n", &axFPGABitStream_red);
+	printk("Address of the bitstream (green): %p\n", &axFPGABitStream_green);
+	printk("Size of the bitstream (red): %d\n", sizeof(axFPGABitStream_red));
+	printk("Size of the bitstream (green): %d\n", sizeof(axFPGABitStream_green));
+#else
 	fpga = device_get_binding("FPGA");
 
 	if (!fpga) {
@@ -38,4 +45,5 @@ void main(void)
 		k_msleep(2000);
 		fpga_reset(fpga);
 	}
+#endif
 }

samples/drivers/fpga/fpga_controller_shell/CMakeLists.txt

@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-cmake_minimum_required(VERSION 3.20.0)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(fpga_controller)
-
-target_sources(app PRIVATE src/main.c)

samples/drivers/fpga/fpga_controller_shell/README.md

@@ -1,68 +0,0 @@
-# Zephyr FPGA controller in shell
-This module is an FPGA driver that can easily load a bitstream, reset it, check its status, enable or disable the FPGA.
-This sample demonstrates how to use the FPGA controller shell subsystem.
-Currently, the sample works with the [QuickLogic QuickFeather board](https://github.com/QuickLogic-Corp/quick-feather-dev-board).
-
-## Requirements
-* Zephyr RTOS with shell subsystem enabled
-* [QuickLogic QuickFeather board](https://github.com/QuickLogic-Corp/quick-feather-dev-board)
-
-## Building
-
-For the QuickLogic QuickFeather board:
-```bash
-west build -b quick_feather samples/drivers/fpga/fpga_controller_shell
-```
-See [QuickFeather programming and debugging](https://docs.zephyrproject.org/latest/boards/arm/quick_feather/doc/index.html#programming-and-debugging) on how to load an image to the board.
-
-## Running
-After connecting to the shell console you should see the following output:
-
-```bash
-Address of the bitstream (red): 0xADDR
-Address of the bitstream (green): 0xADDR
-Size of the bitstream (red): 75960
-Size of the bitstream (green): 75960
-
-uart:~$
-```
-This sample is already prepared with bitstreams.
-After executing the sample, you can see at what address it is stored and its size in bytes.
-
-The FPGA controller command can now be used (`fpga load <device> <address> <size in bytes>`):
-```bash
-uart:~$ fpga load FPGA 0x2001a46c 75960
-FPGA: loading bitstream
-```
-The LED should start blinking (color depending on the selected bitstream).
-To upload the bitstream again you need to reset the FPGA:
-
-```bash
-uart:~$ fpga reset FPGA
-FPGA: resetting FPGA
-```
-You can also use your own bitstream.
-To load a bitstream into device memory, use `devmem load` command.
-It is important to use the -e option when sending a bistream via `xxd`:
-```bash
-uart:~$ devmem load -e 0x10000
-Loading...
-Press ctrl-x + ctrl-q to stop
-```
-Now, the loader is waiting for data.
-You can either type it directly from the console or send it from the host PC (replace `ttyX` with the appropriate one for your shell console):
-```bash
-xxd -p data > /dev/ttyX
-```
-(It is important to use plain-style hex dump)
-Once the data is transferred, use `ctrl-x + ctrl-q` to quit loader.
-It will print the sum of the read bytes and return to the shell:
-```bash
-Number of bytes read: 75960
-uart:~$
-```
-Now the bitstream can be uploaded again.
-```bash
-uart:~$ fpga load FPGA 0x10000 75960
-FPGA: loading bitstream
-```

samples/drivers/fpga/fpga_controller_shell/src/main.c

@@ -1,29 +0,0 @@
-/*
- * Copyright (c) 2021 Antmicro <www.antmicro.com>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/zephyr.h>
-#include <zephyr/shell/shell.h>
-#include <zephyr/device.h>
-#include <zephyr/sys/printk.h>
-#include <zephyr/drivers/fpga.h>
-#include "redled.h"
-#include "greenled.h"
-#include <eoss3_dev.h>
-
-void main(void)
-{
-	IO_MUX->PAD_21_CTRL = (PAD_E_4MA | PAD_P_PULLDOWN | PAD_OEN_NORMAL |
-			       PAD_SMT_DISABLE | PAD_REN_DISABLE | PAD_SR_SLOW |
-			       PAD_CTRL_SEL_AO_REG); /* Enable red led */
-	IO_MUX->PAD_22_CTRL = (PAD_E_4MA | PAD_P_PULLDOWN | PAD_OEN_NORMAL |
-			       PAD_SMT_DISABLE | PAD_REN_DISABLE | PAD_SR_SLOW |
-			       PAD_CTRL_SEL_AO_REG); /* Enable green led */
-
-	printk("Address of the bitstream (red): %p\n", &axFPGABitStream_red);
-	printk("Address of the bitstream (green): %p\n", &axFPGABitStream_green);
-	printk("Size of the bitstream (red): %d\n", sizeof(axFPGABitStream_red));
-	printk("Size of the bitstream (green): %d\n", sizeof(axFPGABitStream_green));
-}