espi: it8xxx2: enable configuration of Chromebook
This enables the below configuration so the AP and EC are able to communicate over eSPI: CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
This commit is contained in:
Dino Li
Anas Nashif
parent
f3c1acaeea
commit
36164c29c1
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@ -21,6 +21,101 @@ config ESPI_PERIPHERAL_HOST_IO
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config ESPI_PERIPHERAL_DEBUG_PORT_80
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default y
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config ESPI_PERIPHERAL_EC_HOST_CMD
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default y
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choice IT8XXX2_H2RAM_HC_SIZE_CHOICE
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prompt "H2RAM space for ec host command"
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default IT8XXX2_H2RAM_HC_SIZE_256
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depends on ESPI_PERIPHERAL_EC_HOST_CMD
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config IT8XXX2_H2RAM_HC_SIZE_16
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bool "16"
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config IT8XXX2_H2RAM_HC_SIZE_32
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bool "32"
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config IT8XXX2_H2RAM_HC_SIZE_64
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bool "64"
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config IT8XXX2_H2RAM_HC_SIZE_128
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bool "128"
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config IT8XXX2_H2RAM_HC_SIZE_256
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bool "256"
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config IT8XXX2_H2RAM_HC_SIZE_512
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bool "512"
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config IT8XXX2_H2RAM_HC_SIZE_1024
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bool "1024"
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config IT8XXX2_H2RAM_HC_SIZE_2048
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bool "2048"
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endchoice
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config ESPI_IT8XXX2_HC_H2RAM_SIZE
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int
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depends on ESPI_PERIPHERAL_EC_HOST_CMD
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default 16 if IT8XXX2_H2RAM_HC_SIZE_16
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default 32 if IT8XXX2_H2RAM_HC_SIZE_32
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default 64 if IT8XXX2_H2RAM_HC_SIZE_64
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default 128 if IT8XXX2_H2RAM_HC_SIZE_128
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default 256 if IT8XXX2_H2RAM_HC_SIZE_256
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default 512 if IT8XXX2_H2RAM_HC_SIZE_512
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default 1024 if IT8XXX2_H2RAM_HC_SIZE_1024
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default 2048 if IT8XXX2_H2RAM_HC_SIZE_2048
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config ESPI_PERIPHERAL_ACPI_SHM_REGION
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default y
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choice IT8XXX2_H2RAM_ACPI_SHM_SIZE_CHOICE
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prompt "H2RAM space for ACPI shared memory region"
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default IT8XXX2_H2RAM_ACPI_SHM_SIZE_256
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depends on ESPI_PERIPHERAL_ACPI_SHM_REGION
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config IT8XXX2_H2RAM_ACPI_SHM_SIZE_16
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bool "16"
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config IT8XXX2_H2RAM_ACPI_SHM_SIZE_32
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bool "32"
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config IT8XXX2_H2RAM_ACPI_SHM_SIZE_64
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bool "64"
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config IT8XXX2_H2RAM_ACPI_SHM_SIZE_128
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bool "128"
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config IT8XXX2_H2RAM_ACPI_SHM_SIZE_256
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bool "256"
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config IT8XXX2_H2RAM_ACPI_SHM_SIZE_512
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bool "512"
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config IT8XXX2_H2RAM_ACPI_SHM_SIZE_1024
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bool "1024"
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config IT8XXX2_H2RAM_ACPI_SHM_SIZE_2048
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bool "2048"
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endchoice
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config ESPI_IT8XXX2_ACPI_SHM_H2RAM_SIZE
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int
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depends on ESPI_PERIPHERAL_ACPI_SHM_REGION
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default 16 if IT8XXX2_H2RAM_ACPI_SHM_SIZE_16
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default 32 if IT8XXX2_H2RAM_ACPI_SHM_SIZE_32
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default 64 if IT8XXX2_H2RAM_ACPI_SHM_SIZE_64
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default 128 if IT8XXX2_H2RAM_ACPI_SHM_SIZE_128
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default 256 if IT8XXX2_H2RAM_ACPI_SHM_SIZE_256
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default 512 if IT8XXX2_H2RAM_ACPI_SHM_SIZE_512
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default 1024 if IT8XXX2_H2RAM_ACPI_SHM_SIZE_1024
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default 2048 if IT8XXX2_H2RAM_ACPI_SHM_SIZE_2048
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config ESPI_PERIPHERAL_CUSTOM_OPCODE
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default y
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config ESPI_FLASH_CHANNEL
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default y
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@ -26,6 +26,7 @@ LOG_MODULE_REGISTER(espi, CONFIG_ESPI_LOG_LEVEL);
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#define IT8XXX2_KBC_OBE_IRQ DT_INST_IRQ_BY_IDX(0, 3, irq)
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#define IT8XXX2_PMC1_IBF_IRQ DT_INST_IRQ_BY_IDX(0, 4, irq)
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#define IT8XXX2_PORT_80_IRQ DT_INST_IRQ_BY_IDX(0, 5, irq)
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#define IT8XXX2_PMC2_IBF_IRQ DT_INST_IRQ_BY_IDX(0, 6, irq)
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/* General Capabilities and Configuration 1 */
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#define IT8XXX2_ESPI_MAX_FREQ_MASK GENMASK(2, 0)
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@ -72,6 +73,7 @@ struct espi_it8xxx2_config {
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uintptr_t base_ec2i;
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uintptr_t base_kbc;
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uintptr_t base_pmc;
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uintptr_t base_smfi;
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};
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struct espi_it8xxx2_data {
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@ -153,6 +155,125 @@ static const struct ec2i_t pmc1_settings[] = {
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{HOST_INDEX_LDA, 0x01},
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};
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#ifdef CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD
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#define IT8XXX2_ESPI_HC_DATA_PORT_MSB \
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((CONFIG_ESPI_PERIPHERAL_HOST_CMD_DATA_PORT_NUM >> 8) & 0xff)
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#define IT8XXX2_ESPI_HC_DATA_PORT_LSB \
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(CONFIG_ESPI_PERIPHERAL_HOST_CMD_DATA_PORT_NUM & 0xff)
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#define IT8XXX2_ESPI_HC_CMD_PORT_MSB \
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(((CONFIG_ESPI_PERIPHERAL_HOST_CMD_DATA_PORT_NUM + 4) >> 8) & 0xff)
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#define IT8XXX2_ESPI_HC_CMD_PORT_LSB \
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((CONFIG_ESPI_PERIPHERAL_HOST_CMD_DATA_PORT_NUM + 4) & 0xff)
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static const struct ec2i_t pmc2_settings[] = {
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/* Select logical device 12h(PM2 host command) */
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{HOST_INDEX_LDN, LDN_PMC2},
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/* I/O Port Base Address (data/command ports) */
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{HOST_INDEX_IOBAD0_MSB, IT8XXX2_ESPI_HC_DATA_PORT_MSB},
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{HOST_INDEX_IOBAD0_LSB, IT8XXX2_ESPI_HC_DATA_PORT_LSB},
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{HOST_INDEX_IOBAD1_MSB, IT8XXX2_ESPI_HC_CMD_PORT_MSB},
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{HOST_INDEX_IOBAD1_LSB, IT8XXX2_ESPI_HC_CMD_PORT_LSB},
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/* Set IRQ=00h for logical device */
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{HOST_INDEX_IRQNUMX, 0x00},
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/* Enable logical device */
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{HOST_INDEX_LDA, 0x01},
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};
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#endif
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#if defined(CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD) || \
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defined(CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION)
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/*
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* Host to RAM (H2RAM) memory mapping.
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* This feature allows host access EC's memory directly by eSPI I/O cycles.
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* Mapping range is 4K bytes and base address is adjustable.
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* Eg. the I/O cycle 800h~8ffh from host can be mapped to x800h~x8ffh.
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* Linker script of h2ram.ld will make the pool 4K aligned.
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*/
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#define IT8XXX2_ESPI_H2RAM_POOL_SIZE 0x1000
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static uint8_t h2ram_pool[IT8XXX2_ESPI_H2RAM_POOL_SIZE]
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__attribute__((section(".h2ram_pool")));
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#if defined(CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION)
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#define H2RAM_ACPI_SHM_MAX ((CONFIG_ESPI_IT8XXX2_ACPI_SHM_H2RAM_SIZE) + \
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(CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION_PORT_NUM))
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#if (H2RAM_ACPI_SHM_MAX > IT8XXX2_ESPI_H2RAM_POOL_SIZE)
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#error "ACPI shared memory region out of h2ram"
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#endif
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#endif /* CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION */
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#if defined(CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD)
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#define H2RAM_EC_HOST_CMD_MAX ((CONFIG_ESPI_IT8XXX2_HC_H2RAM_SIZE) + \
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(CONFIG_ESPI_PERIPHERAL_HOST_CMD_PARAM_PORT_NUM))
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#if (H2RAM_EC_HOST_CMD_MAX > IT8XXX2_ESPI_H2RAM_POOL_SIZE)
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#error "EC host command parameters out of h2ram"
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#endif
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#endif /* CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD */
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#if defined(CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD) && \
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defined(CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION)
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#if (MIN(H2RAM_ACPI_SHM_MAX, H2RAM_EC_HOST_CMD_MAX) > \
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MAX(CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION_PORT_NUM, \
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CONFIG_ESPI_PERIPHERAL_HOST_CMD_PARAM_PORT_NUM))
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#error "ACPI and HC sections of h2ram overlap"
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#endif
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#endif
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#define H2RAM_WINDOW_SIZE(ram_size) ((find_msb_set((ram_size) / 16) - 1) & 0x7)
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static const struct ec2i_t smfi_settings[] = {
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/* Select logical device 0Fh(SMFI) */
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{HOST_INDEX_LDN, LDN_SMFI},
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/* Internal RAM base address on eSPI I/O space */
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{HOST_INDEX_DSLDC6, 0x00},
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/* Enable H2RAM eSPI I/O cycle */
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{HOST_INDEX_DSLDC7, 0x01},
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/* Enable logical device */
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{HOST_INDEX_LDA, 0x01},
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};
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static void smfi_it8xxx2_init(const struct device *dev)
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{
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const struct espi_it8xxx2_config *const config = dev->config;
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struct flash_it8xxx2_regs *const smfi_reg =
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(struct flash_it8xxx2_regs *)config->base_smfi;
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struct gctrl_it8xxx2_regs *const gctrl = ESPI_IT8XXX2_GET_GCTRL_BASE;
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uint8_t h2ram_offset;
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/* Set the host to RAM cycle address offset */
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h2ram_offset = ((uint32_t)h2ram_pool & 0xffff) /
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IT8XXX2_ESPI_H2RAM_POOL_SIZE;
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gctrl->GCTRL_H2ROFSR |= h2ram_offset;
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#ifdef CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD
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memset(&h2ram_pool[CONFIG_ESPI_PERIPHERAL_HOST_CMD_PARAM_PORT_NUM], 0,
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CONFIG_ESPI_IT8XXX2_HC_H2RAM_SIZE);
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/* Set host RAM window 0 base address */
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smfi_reg->SMFI_HRAMW0BA =
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(CONFIG_ESPI_PERIPHERAL_HOST_CMD_PARAM_PORT_NUM >> 4) & 0xff;
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/* Set host RAM window 0 size. (allow R/W) */
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smfi_reg->SMFI_HRAMW0AAS =
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H2RAM_WINDOW_SIZE(CONFIG_ESPI_IT8XXX2_HC_H2RAM_SIZE);
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/* Enable window 0, H2RAM through IO cycle */
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smfi_reg->SMFI_HRAMWC |= (SMFI_H2RAMPS | SMFI_H2RAMW0E);
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#endif
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#ifdef CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION
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memset(&h2ram_pool[CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION_PORT_NUM], 0,
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CONFIG_ESPI_IT8XXX2_ACPI_SHM_H2RAM_SIZE);
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/* Set host RAM window 1 base address */
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smfi_reg->SMFI_HRAMW1BA =
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(CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION_PORT_NUM >> 4) & 0xff;
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/* Set host RAM window 1 size. (read-only) */
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smfi_reg->SMFI_HRAMW1AAS =
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H2RAM_WINDOW_SIZE(CONFIG_ESPI_IT8XXX2_ACPI_SHM_H2RAM_SIZE) |
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SMFI_HRAMWXWPE_ALL;
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/* Enable window 1, H2RAM through IO cycle */
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smfi_reg->SMFI_HRAMWC |= (SMFI_H2RAMPS | SMFI_H2RAMW1E);
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#endif
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}
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#endif /* CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD ||
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* CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION
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*/
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static void ec2i_it8xxx2_wait_status_cleared(const struct device *dev,
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uint8_t mask)
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{
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@ -230,6 +351,13 @@ static void pnpcfg_it8xxx2_init(const struct device *dev)
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if (IS_ENABLED(CONFIG_ESPI_PERIPHERAL_HOST_IO)) {
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PNPCFG(pmc1);
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}
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#ifdef CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD
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PNPCFG(pmc2);
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#endif
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#if defined(CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD) || \
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defined(CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION)
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PNPCFG(smfi);
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#endif
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}
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/* KBC (port 60h/64h) */
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@ -387,6 +515,41 @@ static void port80_it8xxx2_init(const struct device *dev)
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}
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#endif
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#ifdef CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD
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/* PMC 2 (Host command port CONFIG_ESPI_PERIPHERAL_HOST_CMD_DATA_PORT_NUM) */
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static void pmc2_it8xxx2_ibf_isr(const struct device *dev)
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{
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const struct espi_it8xxx2_config *const config = dev->config;
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struct espi_it8xxx2_data *const data = dev->data;
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struct pmc_regs *const pmc_reg = (struct pmc_regs *)config->base_pmc;
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struct espi_event evt = {
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ESPI_BUS_PERIPHERAL_NOTIFICATION,
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ESPI_PERIPHERAL_EC_HOST_CMD,
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ESPI_PERIPHERAL_NODATA
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};
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/* Set processing flag before reading command byte */
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pmc_reg->PM2STS |= PMC_PM2STS_GPF;
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evt.evt_data = pmc_reg->PM2DI;
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espi_send_callbacks(&data->callbacks, dev, evt);
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}
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static void pmc2_it8xxx2_init(const struct device *dev)
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{
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const struct espi_it8xxx2_config *const config = dev->config;
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struct pmc_regs *const pmc_reg = (struct pmc_regs *)config->base_pmc;
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/* Dedicated interrupt for PMC2 */
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pmc_reg->MBXCTRL |= PMC_MBXCTRL_DINT;
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/* Enable pmc2 input buffer full interrupt */
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pmc_reg->PM2CTL |= PMC_PM2CTL_IBFIE;
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IRQ_CONNECT(IT8XXX2_PMC2_IBF_IRQ, 0, pmc2_it8xxx2_ibf_isr,
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DEVICE_DT_INST_GET(0), 0);
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irq_enable(IT8XXX2_PMC2_IBF_IRQ);
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}
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#endif
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/* eSPI api functions */
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#define VW_CHAN(signal, index, level, valid) \
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[signal] = {.vw_index = index, .level_mask = level, .valid_mask = valid}
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@ -616,10 +779,30 @@ static int espi_it8xxx2_read_lpc_request(const struct device *dev,
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case EACPI_READ_STS:
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*data = pmc_reg->PM1STS;
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break;
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#ifdef CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION
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case EACPI_GET_SHARED_MEMORY:
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*data = (uint32_t)&h2ram_pool[
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CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION_PORT_NUM];
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break;
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#endif /* CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION */
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default:
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return -EINVAL;
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}
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} else {
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}
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#ifdef CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE
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else if (op >= ECUSTOM_START_OPCODE && op <= ECUSTOM_MAX_OPCODE) {
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switch (op) {
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case ECUSTOM_HOST_CMD_GET_PARAM_MEMORY:
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*data = (uint32_t)&h2ram_pool[
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CONFIG_ESPI_PERIPHERAL_HOST_CMD_PARAM_PORT_NUM];
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break;
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default:
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return -EINVAL;
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}
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}
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#endif /* CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE */
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else {
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return -ENOTSUP;
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}
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@ -695,7 +878,33 @@ static int espi_it8xxx2_write_lpc_request(const struct device *dev,
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default:
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return -EINVAL;
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}
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} else {
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}
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#ifdef CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE
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else if (op >= ECUSTOM_START_OPCODE && op <= ECUSTOM_MAX_OPCODE) {
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struct pmc_regs *const pmc_reg =
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(struct pmc_regs *)config->base_pmc;
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switch (op) {
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/* Enable/Disable PMC1 (port 62h/66h) interrupt */
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case ECUSTOM_HOST_SUBS_INTERRUPT_EN:
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if (*data) {
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pmc_reg->PM1CTL |= PMC_PM1CTL_IBFIE;
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} else {
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pmc_reg->PM1CTL &= ~PMC_PM1CTL_IBFIE;
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}
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break;
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case ECUSTOM_HOST_CMD_SEND_RESULT:
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/* Write result to data output port (set OBF status) */
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pmc_reg->PM2DO = (*data & 0xff);
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/* Clear processing flag */
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pmc_reg->PM2STS &= ~PMC_PM2STS_GPF;
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break;
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default:
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return -EINVAL;
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}
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}
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#endif /* CONFIG_ESPI_PERIPHERAL_CUSTOM_OPCODE */
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else {
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return -ENOTSUP;
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}
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@ -1606,6 +1815,7 @@ static const struct espi_it8xxx2_config espi_it8xxx2_config_0 = {
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.base_ec2i = DT_INST_REG_ADDR_BY_IDX(0, 4),
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.base_kbc = DT_INST_REG_ADDR_BY_IDX(0, 5),
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.base_pmc = DT_INST_REG_ADDR_BY_IDX(0, 6),
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.base_smfi = DT_INST_REG_ADDR_BY_IDX(0, 7),
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};
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DEVICE_DT_INST_DEFINE(0, &espi_it8xxx2_init, NULL,
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@ -1642,6 +1852,14 @@ static int espi_it8xxx2_init(const struct device *dev)
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/* Accept Port 80h Cycle */
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port80_it8xxx2_init(dev);
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#endif
|
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#if defined(CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD) || \
|
||||
defined(CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION)
|
||||
smfi_it8xxx2_init(dev);
|
||||
#endif
|
||||
#ifdef CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD
|
||||
/* enable pmc2 for host command port */
|
||||
pmc2_it8xxx2_init(dev);
|
||||
#endif
|
||||
|
||||
/* Reset vwidx_cached_flag[] at initialization */
|
||||
espi_it8xxx2_reset_vwidx_cache(dev);
|
||||
|
|
|
|||
|
|
@ -603,13 +603,15 @@
|
|||
0x00f03400 0xc0 /* eSPI Queue 1 */
|
||||
0x00f01200 6 /* EC2I bridge */
|
||||
0x00f01300 11 /* Host KBC */
|
||||
0x00f01500 0x100>; /* Host PMC */
|
||||
0x00f01500 0x100 /* Host PMC */
|
||||
0x00f01000 0xd1>; /* SMFI */
|
||||
interrupts = <IT8XXX2_IRQ_ESPI IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_ESPI_VW IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_KBC_IBF IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_KBC_OBE IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_PMC1_IBF IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_PCH_P80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
IT8XXX2_IRQ_PCH_P80 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_PMC2_IBF IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&intc>;
|
||||
label = "ESPI_0";
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@
|
|||
/* Group 3 */
|
||||
#define IT8XXX2_IRQ_KBC_IBF 24
|
||||
#define IT8XXX2_IRQ_PMC1_IBF 25
|
||||
#define IT8XXX2_IRQ_PMC2_IBF 27
|
||||
#define IT8XXX2_IRQ_TIMER1 30
|
||||
#define IT8XXX2_IRQ_WU21 31
|
||||
/* Group 5 */
|
||||
|
|
|
|||
|
|
@ -7,6 +7,23 @@
|
|||
#include <device.h>
|
||||
#include <soc.h>
|
||||
|
||||
/* SMFI register structure check */
|
||||
IT8XXX2_REG_SIZE_CHECK(flash_it8xxx2_regs, 0xd1);
|
||||
IT8XXX2_REG_OFFSET_CHECK(flash_it8xxx2_regs, SMFI_ECINDAR0, 0x3b);
|
||||
IT8XXX2_REG_OFFSET_CHECK(flash_it8xxx2_regs, SMFI_ECINDAR1, 0x3c);
|
||||
IT8XXX2_REG_OFFSET_CHECK(flash_it8xxx2_regs, SMFI_ECINDAR2, 0x3d);
|
||||
IT8XXX2_REG_OFFSET_CHECK(flash_it8xxx2_regs, SMFI_ECINDAR3, 0x3e);
|
||||
IT8XXX2_REG_OFFSET_CHECK(flash_it8xxx2_regs, SMFI_ECINDDR, 0x3f);
|
||||
IT8XXX2_REG_OFFSET_CHECK(flash_it8xxx2_regs, SMFI_SCAR0L, 0x40);
|
||||
IT8XXX2_REG_OFFSET_CHECK(flash_it8xxx2_regs, SMFI_SCAR0M, 0x41);
|
||||
IT8XXX2_REG_OFFSET_CHECK(flash_it8xxx2_regs, SMFI_SCAR0H, 0x42);
|
||||
IT8XXX2_REG_OFFSET_CHECK(flash_it8xxx2_regs, SMFI_HRAMWC, 0x5a);
|
||||
IT8XXX2_REG_OFFSET_CHECK(flash_it8xxx2_regs, SMFI_HRAMW0BA, 0x5b);
|
||||
IT8XXX2_REG_OFFSET_CHECK(flash_it8xxx2_regs, SMFI_HRAMW1BA, 0x5c);
|
||||
IT8XXX2_REG_OFFSET_CHECK(flash_it8xxx2_regs, SMFI_HRAMW0AAS, 0x5d);
|
||||
IT8XXX2_REG_OFFSET_CHECK(flash_it8xxx2_regs, SMFI_HRAMW1AAS, 0x5e);
|
||||
IT8XXX2_REG_OFFSET_CHECK(flash_it8xxx2_regs, SMFI_FLHCTRL6R, 0xa2);
|
||||
|
||||
/* EC2I register structure check */
|
||||
IT8XXX2_REG_SIZE_CHECK(ec2i_regs, 0x06);
|
||||
IT8XXX2_REG_OFFSET_CHECK(ec2i_regs, IHIOA, 0x00);
|
||||
|
|
@ -30,6 +47,11 @@ IT8XXX2_REG_OFFSET_CHECK(pmc_regs, PM1STS, 0x00);
|
|||
IT8XXX2_REG_OFFSET_CHECK(pmc_regs, PM1DO, 0x01);
|
||||
IT8XXX2_REG_OFFSET_CHECK(pmc_regs, PM1DI, 0x04);
|
||||
IT8XXX2_REG_OFFSET_CHECK(pmc_regs, PM1CTL, 0x06);
|
||||
IT8XXX2_REG_OFFSET_CHECK(pmc_regs, PM2STS, 0x10);
|
||||
IT8XXX2_REG_OFFSET_CHECK(pmc_regs, PM2DO, 0x11);
|
||||
IT8XXX2_REG_OFFSET_CHECK(pmc_regs, PM2DI, 0x14);
|
||||
IT8XXX2_REG_OFFSET_CHECK(pmc_regs, PM2CTL, 0x16);
|
||||
IT8XXX2_REG_OFFSET_CHECK(pmc_regs, MBXCTRL, 0x19);
|
||||
|
||||
/* eSPI slave register structure check */
|
||||
IT8XXX2_REG_SIZE_CHECK(espi_slave_regs, 0xd8);
|
||||
|
|
|
|||
|
|
@ -1459,6 +1459,7 @@ struct peci_it8xxx2_regs {
|
|||
/* Shared Memory Flash Interface Bridge (SMFI) registers */
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
/* TODO: rename flash_it8xxx2_regs to smfi_regs */
|
||||
struct flash_it8xxx2_regs {
|
||||
volatile uint8_t reserved1[59];
|
||||
/* 0x3B: EC-Indirect memory address 0 */
|
||||
|
|
@ -1477,9 +1478,21 @@ struct flash_it8xxx2_regs {
|
|||
volatile uint8_t SMFI_SCAR0M;
|
||||
/* 0x42: Scratch SRAM 0 address high byte */
|
||||
volatile uint8_t SMFI_SCAR0H;
|
||||
volatile uint8_t reserved2[95];
|
||||
volatile uint8_t reserved1_1[23];
|
||||
/* 0x5A: Host RAM Window Control */
|
||||
volatile uint8_t SMFI_HRAMWC;
|
||||
/* 0x5B: Host RAM Window 0 Base Address [11:4] */
|
||||
volatile uint8_t SMFI_HRAMW0BA;
|
||||
/* 0x5C: Host RAM Window 1 Base Address [11:4] */
|
||||
volatile uint8_t SMFI_HRAMW1BA;
|
||||
/* 0x5D: Host RAM Window 0 Access Allow Size */
|
||||
volatile uint8_t SMFI_HRAMW0AAS;
|
||||
/* 0x5E: Host RAM Window 1 Access Allow Size */
|
||||
volatile uint8_t SMFI_HRAMW1AAS;
|
||||
volatile uint8_t reserved2[67];
|
||||
/* 0xA2: Flash control 6 */
|
||||
volatile uint8_t SMFI_FLHCTRL6R;
|
||||
volatile uint8_t reserved3[46];
|
||||
};
|
||||
#endif /* !__ASSEMBLER__ */
|
||||
|
||||
|
|
@ -1494,6 +1507,16 @@ struct flash_it8xxx2_regs {
|
|||
/* Scratch SRAM enable */
|
||||
#define IT8XXX2_SMFI_SCAR0H_ENABLE BIT(3)
|
||||
|
||||
/* H2RAM Path Select. 1b: H2RAM through LPC IO cycle. */
|
||||
#define SMFI_H2RAMPS BIT(4)
|
||||
/* H2RAM Window 1 Enable */
|
||||
#define SMFI_H2RAMW1E BIT(1)
|
||||
/* H2RAM Window 0 Enable */
|
||||
#define SMFI_H2RAMW0E BIT(0)
|
||||
|
||||
/* Host RAM Window x Write Protect Enable (All protected) */
|
||||
#define SMFI_HRAMWXWPE_ALL (BIT(5) | BIT(4))
|
||||
|
||||
/* --- GPIO --- */
|
||||
#define IT8XXX2_GPIO_BASE 0x00F01600
|
||||
#define IT8XXX2_GPIO2_BASE 0x00F03E00
|
||||
|
|
@ -2105,8 +2128,30 @@ struct pmc_regs {
|
|||
volatile uint8_t PM1IE;
|
||||
/* 0x09-0x0f: Reserved1 */
|
||||
volatile uint8_t reserved1[7];
|
||||
/* 0x10-0xff: Reserved2 */
|
||||
volatile uint8_t reserved2[0xf0];
|
||||
/* 0x10: Host Interface PM Channel 2 Status */
|
||||
volatile uint8_t PM2STS;
|
||||
/* 0x11: Host Interface PM Channel 2 Data Out Port */
|
||||
volatile uint8_t PM2DO;
|
||||
/* 0x12: Host Interface PM Channel 2 Data Out Port with SCI# */
|
||||
volatile uint8_t PM2DOSCI;
|
||||
/* 0x13: Host Interface PM Channel 2 Data Out Port with SMI# */
|
||||
volatile uint8_t PM2DOSMI;
|
||||
/* 0x14: Host Interface PM Channel 2 Data In Port */
|
||||
volatile uint8_t PM2DI;
|
||||
/* 0x15: Host Interface PM Channel 2 Data In Port with SCI# */
|
||||
volatile uint8_t PM2DISCI;
|
||||
/* 0x16: Host Interface PM Channel 2 Control */
|
||||
volatile uint8_t PM2CTL;
|
||||
/* 0x17: Host Interface PM Channel 2 Interrupt Control */
|
||||
volatile uint8_t PM2IC;
|
||||
/* 0x18: Host Interface PM Channel 2 Interrupt Enable */
|
||||
volatile uint8_t PM2IE;
|
||||
/* 0x19: Mailbox Control */
|
||||
volatile uint8_t MBXCTRL;
|
||||
/* 0x1a-0x1f: Reserved2 */
|
||||
volatile uint8_t reserved2[6];
|
||||
/* 0x20-0xff: Reserved3 */
|
||||
volatile uint8_t reserved3[0xe0];
|
||||
};
|
||||
|
||||
/* Input Buffer Full Interrupt Enable */
|
||||
|
|
@ -2120,6 +2165,24 @@ struct pmc_regs {
|
|||
/* A2 Address (A2) */
|
||||
#define PMC_PM1STS_A2_ADDR BIT(3)
|
||||
|
||||
/* PMC2 Input Buffer Full Interrupt Enable */
|
||||
#define PMC_PM2CTL_IBFIE BIT(0)
|
||||
/* General Purpose Flag */
|
||||
#define PMC_PM2STS_GPF BIT(2)
|
||||
|
||||
/*
|
||||
* Dedicated Interrupt
|
||||
* 0b:
|
||||
* INT3: PMC Output Buffer Empty Int
|
||||
* INT25: PMC Input Buffer Full Int
|
||||
* 1b:
|
||||
* INT3: PMC1 Output Buffer Empty Int
|
||||
* INT25: PMC1 Input Buffer Full Int
|
||||
* INT26: PMC2 Output Buffer Empty Int
|
||||
* INT27: PMC2 Input Buffer Full Int
|
||||
*/
|
||||
#define PMC_MBXCTRL_DINT BIT(5)
|
||||
|
||||
/*
|
||||
* eSPI slave registers
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -1,3 +1,10 @@
|
|||
zephyr_sources(
|
||||
soc.c
|
||||
)
|
||||
|
||||
# IMPORTANT:
|
||||
# The h2ram section must be first added to RAM_SECTIONS to avoid gap.
|
||||
zephyr_linker_sources_ifdef(CONFIG_ESPI_IT8XXX2
|
||||
RAM_SECTIONS
|
||||
h2ram.ld
|
||||
)
|
||||
|
|
|
|||
19
soc/riscv/riscv-ite/it8xxx2/h2ram.ld
Normal file
19
soc/riscv/riscv-ite/it8xxx2/h2ram.ld
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
/*
|
||||
* Copyright (c) 2022 ITE Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
SECTION_PROLOGUE(.h2ram_pool, (NOLOAD),)
|
||||
{
|
||||
/*
|
||||
* Ensure this secation is 4k-byte aligned.
|
||||
* NOTE: This won't cause gap if this is included first inside
|
||||
* the RAMABLE_REGION. Because RAM base is 4k-byte aligned.
|
||||
*/
|
||||
. = ALIGN(0x1000);
|
||||
_h2ram_pool_start = .;
|
||||
KEEP(*(.h2ram_pool))
|
||||
_h2ram_pool_end = .;
|
||||
} GROUP_LINK_IN(RAMABLE_REGION)
|
||||
_h2ram_pool_size = ABSOLUTE(_h2ram_pool_end - _h2ram_pool_start);
|
||||
Loading…
Reference in a new issue