ARC: add nsim_hs6x_smp board with 2 cores ARCv3 HS6x

Add nsim_hs6x_smp simulation board (nSIM based) with
2 cores ARCv3 HS6x CPU.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>

boards/arc/nsim/board.cmake

@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: Apache-2.0
 set(EMU_PLATFORM nsim)
 
-if(NOT CONFIG_SOC_NSIM_HS_SMP)
+if(NOT (CONFIG_SOC_NSIM_HS_SMP OR CONFIG_SOC_NSIM_HS6X_SMP))
 board_set_flasher_ifnset(arc-nsim)
 board_set_debugger_ifnset(arc-nsim)
 endif()
@@ -23,6 +23,8 @@ board_runner_args(mdb-nsim "--cores=${CONFIG_MP_NUM_CPUS}" "--nsim_args=mdb_hs_s
 elseif(${CONFIG_SOC_NSIM_HS6X})
 board_runner_args(arc-nsim "--props=nsim_hs6x.props")
 board_runner_args(mdb-nsim "--nsim_args=mdb_hs6x.args")
+elseif(${CONFIG_SOC_NSIM_HS6X_SMP})
+board_runner_args(mdb-nsim "--cores=${CONFIG_MP_NUM_CPUS}" "--nsim_args=mdb_hs6x_smp.args")
 endif()
 
 board_finalize_runner_args(arc-nsim)

boards/arc/nsim/nsim_hs6x_smp.dts

@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2021, Synopsys, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include "nsim.dtsi"
+
+/ {
+	model = "snps,nsim_hs";
+	compatible = "snps,nsim_hs";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "snps,arcv3-hs";
+			reg = <0>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "snps,arcv3-hs";
+			reg = <1>;
+		};
+	};
+};

boards/arc/nsim/nsim_hs6x_smp.yaml

@@ -0,0 +1,11 @@
+identifier: nsim_hs6x_smp
+name: Multi-core HS6x nSIM simulator
+type: mcu
+simulation: mdb-nsim
+arch: arc
+toolchain:
+  - cross-compile
+testing:
+  ignore_tags:
+    - net
+    - bluetooth

boards/arc/nsim/nsim_hs6x_smp_defconfig

@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_ISA_ARCV3=y
+CONFIG_SOC_NSIM=y
+CONFIG_SOC_NSIM_HS6X_SMP=y
+CONFIG_BOARD_NSIM=y
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
+CONFIG_XIP=n
+CONFIG_BUILD_OUTPUT_BIN=n
+CONFIG_PRINTK=y
+CONFIG_ARCV2_INTERRUPT_UNIT=y
+CONFIG_ARCV2_TIMER=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_ARC_EXCEPTION_DEBUG=y
+CONFIG_SMP=y
+CONFIG_MP_NUM_CPUS=2

boards/arc/nsim/support/mdb_hs6x_smp.args

@@ -0,0 +1,31 @@
+	-arc64
+	-nogoifmain
+	-Xatomic
+	-Xtimer0
+	-Xtimer1
+	-Xdiv_rem
+	-Xunaligned
+	-prop=nsim_isa_addr_size=64
+	-prop=nsim_isa_pc_size=64
+	-prop=nsim_isa_vec64=1
+	-dcache=65536,64,2,a
+	-dcache_feature=2
+	-dcache_uncached_region
+	-dcache_mem_cycles=2
+	-icache=65536,64,4,a
+	-icache_feature=2
+	-arconnect
+	-connect_ics=1
+	-connect_ics_num_semas=16
+	-connect_icm=1
+	-connect_icm_sram_size=512
+	-connect_icm_sram_prot=none
+	-connect_pmu=1
+	-connect_idu=2
+	-connect_idu_cirqnum=64
+	-connect_gfrc=1
+	-connect_icd=2
+	-connect_ici=2
+	-noprofile
+	-prop=nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=0,use_connect=1
+	-instrs_per_pass=512

cmake/emu/nsim.cmake

@@ -1,5 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
-if(${CONFIG_SOC_NSIM_HS_SMP})
+if((${CONFIG_SOC_NSIM_HS_SMP}) OR (${CONFIG_SOC_NSIM_HS6X_SMP}))
 # mdb is required to run nsim multicore targets
 find_program(
   MDB
@@ -8,6 +8,8 @@ find_program(
 
 if(${CONFIG_SOC_NSIM_HS_SMP})
  set(MDB_ARGS mdb_hs_smp.args)
+elseif(${CONFIG_SOC_NSIM_HS6X_SMP})
+ set(MDB_ARGS mdb_hs6x_smp.args)
 endif()
 
 add_custom_target(run

soc/arc/snps_nsim/Kconfig

@@ -32,4 +32,7 @@ config SOC_NSIM_HS_SMP
 config SOC_NSIM_HS6X
 	bool "Synopsys ARC HS6x in nSIM"
 
+config SOC_NSIM_HS6X_SMP
+	bool "Multi-core Synopsys ARC HS6x in nSIM"
+
 endchoice

soc/arc/snps_nsim/Kconfig.defconfig

@@ -18,5 +18,6 @@ source "soc/arc/snps_nsim/Kconfig.defconfig.sem"
 source "soc/arc/snps_nsim/Kconfig.defconfig.hs"
 source "soc/arc/snps_nsim/Kconfig.defconfig.hs_smp"
 source "soc/arc/snps_nsim/Kconfig.defconfig.hs6x"
+source "soc/arc/snps_nsim/Kconfig.defconfig.hs6x_smp"
 
 endif # SOC_NSIM

soc/arc/snps_nsim/Kconfig.defconfig.hs6x_smp

@@ -0,0 +1,33 @@
+# Copyright (c) 2021 Synopsys, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_NSIM_HS6X_SMP
+
+config CPU_HS6X
+	default y
+
+config NUM_IRQ_PRIO_LEVELS
+	# This processor supports 16 priority levels:
+	default 2
+
+config NUM_IRQS
+	# must be > the highest interrupt number used
+	default 30
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	# SMP simulation is slower than single core, 1 Mhz seems reasonable match with wallclock
+	default 1000000
+
+config CACHE_MANAGEMENT
+	default y
+
+config HARVARD
+	default y
+
+config ARC_CONNECT
+	default y
+
+config MP_NUM_CPUS
+	default 2
+
+endif # SOC_NSIM_HS6X_SMP