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soc: xtensa: esp32: fix app cpu boot

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procedure by setting its PC to 0 before reset.

Signed-off-by: Felipe Neves <felipe.neves@linaro.org>
This commit is contained in:
Felipe Neves 2022-07-28 21:20:38 -03:00 committed by Carles Cufí
parent a5379b71f8
commit 382b4144e3
2 changed files with 6 additions and 4 deletions
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8
cmake/toolchain/espressif/target.cmake
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@ -8,10 +8,10 @@ set(COMPILER gcc)
set(LINKER ld)
set(BINTOOLS gnu)
set(CROSS_COMPILE_TARGET_xtensa_esp32 xtensa-esp32-elf)
set(CROSS_COMPILE_TARGET_xtensa_esp32_net xtensa-esp32-elf)
set(CROSS_COMPILE_TARGET_xtensa_esp32s2 xtensa-esp32s2-elf)
set(CROSS_COMPILE_TARGET_riscv_esp32c3 riscv32-esp-elf)
set(CROSS_COMPILE_TARGET_xtensa_esp32 xtensa-esp32-elf)
set(CROSS_COMPILE_TARGET_xtensa_esp32_net xtensa-esp32-elf)
set(CROSS_COMPILE_TARGET_xtensa_esp32s2 xtensa-esp32s2-elf)
set(CROSS_COMPILE_TARGET_riscv_esp32c3 riscv32-esp-elf)
set(CROSS_COMPILE_TARGET ${CROSS_COMPILE_TARGET_${ARCH}_${CONFIG_SOC}})
set(SYSROOT_TARGET ${CROSS_COMPILE_TARGET})

2
soc/xtensa/esp32/esp32-mp.c
View file

@ -183,6 +183,8 @@ void esp_appcpu_start(void *entry_point)
esp_rom_Cache_Flush(1);
esp_rom_Cache_Read_Enable(1);
esp_rom_ets_set_appcpu_boot_addr((void *)0);
RTC_CNTL_SW_CPU_STALL &= ~RTC_CNTL_SW_STALL_APPCPU_C1;
RTC_CNTL_OPTIONS0 &= ~RTC_CNTL_SW_STALL_APPCPU_C0;
DPORT_APPCPU_CTRL_B |= DPORT_APPCPU_CLKGATE_EN;