dts: x86: intel: Move SoC devicetree includes under a vendor directory

Cleans up SoC devicetree include file locations to follow the convention
of dts/<arch>/<vendor>/

Signed-off-by: Maureen Helm <maureen.helm@intel.com>

boards/x86/acrn/acrn.dts

@@ -11,7 +11,7 @@
 #define DT_DRAM_SIZE	DT_SIZE_K(8192)
 #define DT_DRAM_BASE	0
 
-#include <ia32.dtsi>
+#include <intel/ia32.dtsi>
 
 / {
 	model = "ACRN";

boards/x86/ehl_crb/ehl_crb.dts

@@ -10,7 +10,7 @@
 
 #define DT_DRAM_SIZE		DT_SIZE_M(2048)
 
-#include <elkhart_lake.dtsi>
+#include <intel/elkhart_lake.dtsi>
 
 / {
 	model = "ehl_crb";

boards/x86/ehl_crb/ehl_crb_sbl.dts

@@ -10,7 +10,7 @@
 
 #define DT_DRAM_SIZE		DT_SIZE_M(2048)
 
-#include <elkhart_lake.dtsi>
+#include <intel/elkhart_lake.dtsi>
 
 &uart2 {
 	status = "disabled";

boards/x86/qemu_x86/qemu_x86.dts

@@ -12,7 +12,7 @@
 #endif
 #define DT_FLASH_SIZE		DT_SIZE_K(4096)
 
-#include <ia32.dtsi>
+#include <intel/ia32.dtsi>
 
 / {
 	model = "QEMU X86 emulator";

boards/x86/qemu_x86/qemu_x86_lakemont.dts

@@ -15,7 +15,7 @@
 #define DT_DRAM_SIZE		DT_SIZE_K(4096)
 #endif
 
-#include <lakemont.dtsi>
+#include <intel/lakemont.dtsi>
 
 / {
 	model = "QEMU X86 (Lakemont) emulator";

boards/x86/up_squared/up_squared.dts

@@ -10,7 +10,7 @@
 
 #define DT_DRAM_SIZE		DT_SIZE_M(2048)
 
-#include <apollo_lake.dtsi>
+#include <intel/apollo_lake.dtsi>
 
 / {
 	model = "up_squared";