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boards: arm: Add initial support for nRF54H20 PDK

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Add targets that allows building for the Application and Radio cores
in the nRF54H20 SoC on the nRF54H20 PDK board.

Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit is contained in:
Andrzej Głąbek 2024-01-23 17:54:45 +01:00 committed by Carles Cufí
parent 6b987d3192
commit 38520a93d3
13 changed files with 595 additions and 0 deletions
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boards/arm/nrf54h20pdk_nrf54h20/Kconfig.board Normal file
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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
config BOARD_NRF54H20PDK_NRF54H20_CPUAPP
bool "nRF54H20 PDK nRF54H20 Application MCU"
depends on SOC_NRF54H20_ENGA_CPUAPP
config BOARD_NRF54H20PDK_NRF54H20_CPURAD
bool "nRF54H20 PDK nRF54H20 Radio MCU"
depends on SOC_NRF54H20_ENGA_CPURAD

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boards/arm/nrf54h20pdk_nrf54h20/Kconfig.defconfig Normal file
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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
config BOARD
default "nrf54h20pdk_nrf54h20_cpuapp" if BOARD_NRF54H20PDK_NRF54H20_CPUAPP
default "nrf54h20pdk_nrf54h20_cpurad" if BOARD_NRF54H20PDK_NRF54H20_CPURAD
if BOARD_NRF54H20PDK_NRF54H20_CPUAPP || BOARD_NRF54H20PDK_NRF54H20_CPURAD
# Data cache is disabled due to a HW issue in the EngA SoC revision.
config DCACHE
default n
endif # BOARD_NRF54H20PDK_NRF54H20_CPUAPP || BOARD_NRF54H20PDK_NRF54H20_CPURAD

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# SPDX-License-Identifier: Apache-2.0
include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)

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.. _nrf54h20pdk_nrf54h20:
nRF54H20 PDK
############
Overview
********
The nRF54H20 PDK is a single-board preview development kit for evaluation
and development on the Nordic nRF54H20 System-on-Chip (SoC).
The nRF54H20 is a multicore SoC with:
* an Arm Cortex-M33 core with DSP instructions, FPU, and Armv8-M Security
Extensions, running at up to 320 MHz, referred to as the **application core**
* an Arm Cortex-M33 core with DSP instructions, FPU, and Armv8-M Security
Extensions, running at up to 256 MHz, referred to as the **radio core**.
The ``nrf54h20pdk_nrf54h20_cpuapp`` build target provides support for
the application core on the nRF54H20 SoC.
The ``nrf54h20pdk_nrf54h20_cpurad`` build target provides support for
the radio core on the nRF54H20 SoC.
nRF54H20 SoC provides support for the following devices:
* :abbr:`ADC (Analog to Digital Converter)`
* CLOCK
* :abbr:`GPIO (General Purpose Input Output)`
* :abbr:`GPIOTE (General Purpose Input Output tasks and events)`
* :abbr:`GRTC (Global real-time counter)`
* :abbr:`I2C (Inter-Integrated Circuit)`
* MRAM
* :abbr:`PWM (Pulse Width Modulation)`
* RADIO (Bluetooth Low Energy and 802.15.4)
* :abbr:`SPI (Serial Peripheral Interface)`
* :abbr:`UART (Universal asynchronous receiver-transmitter)`
* :abbr:`USB (Universal Serial Bus)`
* :abbr:`WDT (Watchdog Timer)`
.. figure:: img/nrf54h20pdk_nrf54h20.webp
:align: center
:alt: nRF54H20 PDK
nRF54H20 PDK (Credit: Nordic Semiconductor)
Hardware
********
nRF54H20 PDK has two crystal oscillators:
* High-frequency 32 MHz crystal oscillator (HFXO)
* Low-frequency 32.768 kHz crystal oscillator (LFXO)
Supported Features
==================
The nrf54h20pdk_nrf54h20_cpuapp board configuration supports the following
hardware features:
+-----------+------------+----------------------+
| Interface | Controller | Driver/Component |
+===========+============+======================+
| GPIO | on-chip | gpio |
+-----------+------------+----------------------+
| GPIOTE | on-chip | gpio |
+-----------+------------+----------------------+
| GRTC | on-chip | system clock |
+-----------+------------+----------------------+
| UART | on-chip | serial |
+-----------+------------+----------------------+
The nrf54h20pdk_nrf54h20_cpurad board configuration supports the following
hardware features:
+-----------+------------+----------------------+
| Interface | Controller | Driver/Component |
+===========+============+======================+
| GPIO | on-chip | gpio |
+-----------+------------+----------------------+
| GPIOTE | on-chip | gpio |
+-----------+------------+----------------------+
| GRTC | on-chip | system clock |
+-----------+------------+----------------------+
| UARTE | on-chip | serial |
+-----------+------------+----------------------+
Other hardware features have not been enabled yet for this board.
Connections and IOs
===================
LEDs
----
* LED1 (green) = P9.0
* LED2 (green) = P9.1
* LED3 (green) = P9.2
* LED4 (green) = P9.3
Push buttons
------------
* BUTTON1 = P0.8
* BUTTON2 = P0.9
* BUTTON3 = P0.10
* BUTTON4 = P0.11
* RESET (SW1)
Programming and Debugging
*************************
Applications for both the ``nrf54h20pdk_nrf54h20_cpuapp`` and
``nrf54h20pdk_nrf54h20_cpurad`` targets can be built, flashed,
and debugged in the usual way. See :ref:`build_an_application`
and :ref:`application_run` for more details on building and running.
Flashing
========
As an example, this section shows how to build and flash the :ref:`hello_world`
application.
Follow the instructions in the :ref:`nordic_segger` page to install
and configure all the necessary software. Further information can be
found in :ref:`nordic_segger_flashing`.
To build and program the sample to the nRF54H20 PDK, complete the following steps:
First, connect the nRF54H20 PDK to you computer using the IMCU USB port on the PDK.
Next, build the sample by running the following command:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: nrf54h20pdk_nrf54h20_cpuapp
:goals: build flash
Testing the LEDs and buttons in the nRF54H20 PDK
************************************************
There are 2 samples that allow you to test that the buttons (switches) and LEDs
on the board are working properly with Zephyr:
* :zephyr:code-sample:`blinky`
* :zephyr:code-sample:`button`
You can build and flash the examples to make sure Zephyr is running correctly on
your board. The button and LED definitions can be found in
:zephyr_file:`boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp.dts`.

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boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20-memory_map.dtsi Normal file
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/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/ {
reserved-memory {
cpuppr_ram3x_region: memory@2fc00000 {
compatible = "nordic,owned-memory";
reg = <0x2fc00000 DT_SIZE_K(28)>;
status = "disabled";
perm-read;
perm-write;
perm-execute;
};
ram3x_dma_region: memory@2fc07000 {
compatible = "nordic,owned-memory";
reg = <0x2fc07000 DT_SIZE_K(4)>;
status = "disabled";
perm-read;
perm-write;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2fc07000 0x1000>;
cpuapp_dma_region: memory@680 {
compatible = "zephyr,memory-region";
reg = <0x680 DT_SIZE_K(2)>;
status = "disabled";
#memory-region-cells = <0>;
zephyr,memory-region = "DMA_RAM3x_APP";
};
cpurad_dma_region: memory@e80 {
compatible = "zephyr,memory-region";
reg = <0xe80 0x80>;
status = "disabled";
#memory-region-cells = <0>;
zephyr,memory-region = "DMA_RAM3x_RAD";
};
};
};
};
&mram1x {
cpurad_rx_partitions: cpurad-rx-partitions {
compatible = "nordic,owned-partitions", "fixed-partitions";
status = "disabled";
perm-read;
perm-execute;
perm-secure;
#address-cells = <1>;
#size-cells = <1>;
cpurad_slot0_partition: partition@66000 {
reg = <0x66000 DT_SIZE_K(256)>;
};
};
cpuapp_rx_partitions: cpuapp-rx-partitions {
compatible = "nordic,owned-partitions", "fixed-partitions";
status = "disabled";
perm-read;
perm-execute;
perm-secure;
#address-cells = <1>;
#size-cells = <1>;
cpuapp_slot0_partition: partition@a6000 {
reg = <0xa6000 DT_SIZE_K(512)>;
};
cpuppr_code_partition: partition@126000 {
reg = <0x126000 DT_SIZE_K(28)>;
};
};
};

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boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20-pinctrl.dtsi Normal file
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/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
&pinctrl {
/omit-if-no-ref/ uart135_default: uart135_default {
group1 {
psels = <NRF_PSEL(UART_TX, 1, 4)>,
<NRF_PSEL(UART_RTS, 1, 0)>;
};
group2 {
bias-pull-up;
psels = <NRF_PSEL(UART_RX, 1, 5)>,
<NRF_PSEL(UART_CTS, 1, 6)>;
};
};
/omit-if-no-ref/ uart135_sleep: uart135_sleep {
group1 {
low-power-enable;
psels = <NRF_PSEL(UART_TX, 1, 4)>,
<NRF_PSEL(UART_RX, 1, 5)>,
<NRF_PSEL(UART_RTS, 1, 0)>,
<NRF_PSEL(UART_CTS, 1, 6)>;
};
};
/omit-if-no-ref/ uart136_default: uart136_default {
group1 {
psels = <NRF_PSEL(UART_TX, 2, 4)>,
<NRF_PSEL(UART_RTS, 2, 0)>;
};
group2 {
bias-pull-up;
psels = <NRF_PSEL(UART_RX, 2, 5)>,
<NRF_PSEL(UART_CTS, 2, 6)>;
};
};
/omit-if-no-ref/ uart136_sleep: uart136_sleep {
group1 {
low-power-enable;
psels = <NRF_PSEL(UART_TX, 2, 4)>,
<NRF_PSEL(UART_RX, 2, 5)>,
<NRF_PSEL(UART_RTS, 2, 0)>,
<NRF_PSEL(UART_CTS, 2, 6)>;
};
};
};

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boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp.dts Normal file
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/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <nordic/nrf54h20_enga_cpuapp.dtsi>
#include "nrf54h20pdk_nrf54h20-memory_map.dtsi"
#include "nrf54h20pdk_nrf54h20-pinctrl.dtsi"
/ {
compatible = "nordic,nrf54h20pdk_nrf54h20-cpuapp";
model = "Nordic nRF54H20 PDK nRF54H20 Application MCU";
chosen {
zephyr,console = &uart136;
zephyr,code-partition = &cpuapp_slot0_partition;
zephyr,flash = &mram1x;
zephyr,sram = &cpuapp_ram0;
};
aliases {
led0 = &led0;
led1 = &led1;
led2 = &led2;
led3 = &led3;
sw0 = &button0;
sw1 = &button1;
sw2 = &button2;
sw3 = &button3;
};
buttons {
compatible = "gpio-keys";
button0: button_0 {
gpios = <&gpio0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button 0";
zephyr,code = <INPUT_KEY_0>;
};
button1: button_1 {
gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button 1";
zephyr,code = <INPUT_KEY_1>;
};
button2: button_2 {
gpios = <&gpio0 10 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button 2";
zephyr,code = <INPUT_KEY_2>;
};
button3: button_3 {
gpios = <&gpio0 11 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button 3";
zephyr,code = <INPUT_KEY_3>;
};
};
leds {
compatible = "gpio-leds";
led0: led_0 {
gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>;
label = "Green LED 0";
};
led1: led_1 {
gpios = <&gpio9 1 GPIO_ACTIVE_HIGH>;
label = "Green LED 1";
};
led2: led_2 {
gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>;
label = "Green LED 2";
};
led3: led_3 {
gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>;
label = "Green LED 3";
};
};
};
&ram3x_dma_region {
status = "okay";
};
&cpuapp_dma_region {
status = "okay";
};
&cpuapp_rx_partitions {
status = "okay";
};
&cpuppr_vpr {
source-memory = <&cpuppr_code_partition>;
execution-memory = <&cpuppr_ram3x_region>;
};
&gpiote130 {
status = "okay";
owned-channels = <0 1 2 3 4 5 6 7>;
};
&gpio0 {
status = "okay";
};
&gpio9 {
status = "okay";
};
&grtc {
status = "okay";
child-owned-channels = <5 6>;
nonsecure-channels = <5 6>;
owned-channels = <4 5 6>;
};
&uart135 {
pinctrl-0 = <&uart135_default>;
pinctrl-1 = <&uart135_sleep>;
pinctrl-names = "default", "sleep";
};
&uart136 {
status = "okay";
memory-regions = <&cpuapp_dma_region>;
pinctrl-0 = <&uart136_default>;
pinctrl-1 = <&uart136_sleep>;
pinctrl-names = "default", "sleep";
};

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boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp.yaml Normal file
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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
identifier: nrf54h20pdk_nrf54h20_cpuapp
name: nRF54H20-PDK-nRF54H20-Application
type: mcu
arch: arm
toolchain:
- gnuarmemb
- xtools
- zephyr
ram: 32
flash: 368
supported:
- gpio

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boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp_defconfig Normal file
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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
CONFIG_SOC_SERIES_NRF54HX=y
CONFIG_SOC_NRF54H20=y
CONFIG_SOC_NRF54H20_ENGA_CPUAPP=y
CONFIG_BOARD_NRF54H20PDK_NRF54H20_CPUAPP=y
CONFIG_USE_DT_CODE_PARTITION=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# MPU-based null-pointer dereferencing detection cannot be applied
# as the (0x0 - 0x400) region is unmapped for this target.
CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
# Enable cache
CONFIG_CACHE_MANAGEMENT=y
CONFIG_EXTERNAL_CACHE=y
# Enable GPIO
CONFIG_GPIO=y
# Enable UART driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y

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/*
* Copyright (c) 2024 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <nordic/nrf54h20_enga_cpurad.dtsi>
#include "nrf54h20pdk_nrf54h20-memory_map.dtsi"
#include "nrf54h20pdk_nrf54h20-pinctrl.dtsi"
/ {
compatible = "nordic,nrf54h20pdk_nrf54h20-cpurad";
model = "Nordic nRF54H20 PDK nRF54H20 Radio MCU";
chosen {
zephyr,console = &uart135;
zephyr,code-partition = &cpurad_slot0_partition;
zephyr,flash = &mram1x;
zephyr,sram = &cpurad_ram0;
};
};
&ram3x_dma_region {
status = "okay";
};
&cpurad_dma_region {
status = "okay";
};
&cpurad_rx_partitions {
status = "okay";
};
&grtc {
status = "okay";
child-owned-channels = <8 9 10 11 12>;
interrupts = <109 NRF_DEFAULT_IRQ_PRIORITY>,
<108 NRF_DEFAULT_IRQ_PRIORITY>;
nonsecure-channels = <8 9 10 11 12>;
owned-channels = <7 8 9 10 11 12 13 14>;
};
&uart135 {
status = "okay";
memory-regions = <&cpurad_dma_region>;
pinctrl-0 = <&uart135_default>;
pinctrl-1 = <&uart135_sleep>;
pinctrl-names = "default", "sleep";
};
&uart136 {
pinctrl-0 = <&uart136_default>;
pinctrl-1 = <&uart136_sleep>;
pinctrl-names = "default", "sleep";
};

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boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad.yaml Normal file
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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
identifier: nrf54h20pdk_nrf54h20_cpurad
name: nRF54H20-PDK-nRF54H20-Radio
type: mcu
arch: arm
toolchain:
- gnuarmemb
- xtools
- zephyr
ram: 32
flash: 368
supported:
- gpio

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boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad_defconfig Normal file
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# Copyright (c) 2024 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
CONFIG_SOC_SERIES_NRF54HX=y
CONFIG_SOC_NRF54H20=y
CONFIG_SOC_NRF54H20_ENGA_CPURAD=y
CONFIG_BOARD_NRF54H20PDK_NRF54H20_CPURAD=y
CONFIG_USE_DT_CODE_PARTITION=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# MPU-based null-pointer dereferencing detection cannot be applied
# as the (0x0 - 0x400) region is unmapped for this target.
CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
# Enable cache
CONFIG_CACHE_MANAGEMENT=y
CONFIG_EXTERNAL_CACHE=y
# Enable UART driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y