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soc: arm: st_stm32: stm32mp1: Add SPI support

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Add SPI support for STM32MP1x SoC.

Signed-off-by: Yaël Boutreux <yael.boutreux@st.com>
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
This commit is contained in:
Yaël Boutreux 2019-08-01 13:57:30 +02:00 committed by Maureen Helm
parent 2f334817b0
commit 3a967f92c3
3 changed files with 133 additions and 0 deletions
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18
drivers/pinmux/stm32/pinmux_stm32mp1x.h
View file

@ -38,5 +38,23 @@
(STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)
#define STM32MP1X_PINMUX_FUNC_PE10_UART7_CTS \
(STM32_PINMUX_ALT_FUNC_7 | STM32_PUSHPULL_PULLUP)
#define STM32MP1X_PINMUX_FUNC_PE11_SPI4_NSS \
(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
#define STM32MP1X_PINMUX_FUNC_PE12_SPI4_SCK \
(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
#define STM32MP1X_PINMUX_FUNC_PE13_SPI4_MISO \
(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
#define STM32MP1X_PINMUX_FUNC_PE14_SPI4_MOSI \
(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
/* Port F */
#define STM32MP1X_PINMUX_FUNC_PF6_SPI5_NSS \
(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
#define STM32MP1X_PINMUX_FUNC_PF7_SPI5_SCK \
(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
#define STM32MP1X_PINMUX_FUNC_PF8_SPI5_MISO \
(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
#define STM32MP1X_PINMUX_FUNC_PF9_SPI5_MOSI \
(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
#endif /* ZEPHYR_DRIVERS_PINMUX_STM32_PINMUX_STM32MP1X_H_ */

50
dts/arm/st/mp1/stm32mp157.dtsi
View file

@ -148,6 +148,56 @@
};
};
spi1: spi@44004000 {
compatible = "st,stm32-spi-fifo";
reg = <0x44004000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x100>;
interrupts = <35 5>;
label = "SPI_1";
};
spi2: spi@4400b000 {
compatible = "st,stm32-spi-fifo";
reg = <0x4400b000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x800>;
interrupts = <36 5>;
label = "SPI_2";
};
spi3: spi@4400c000 {
compatible = "st,stm32-spi-fifo";
reg = <0x4400c000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x1000>;
interrupts = <51 5>;
label = "SPI_3";
};
spi4: spi@44005000 {
compatible = "st,stm32-spi-fifo";
reg = <0x44005000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x200>;
interrupts = <84 5>;
label = "SPI_4";
};
spi5: spi@44009000 {
compatible = "st,stm32-spi-fifo";
reg = <0x44009000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x400>;
interrupts = <85 5>;
label = "SPI_5";
};
usart2: serial@4000e000 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x4000e000 0x400>;

65
soc/arm/st_stm32/stm32mp1/dts_fixup.h
View file

@ -195,6 +195,71 @@
#define DT_GPIO_STM32_GPIOK_CLOCK_BUS \
DT_ST_STM32_GPIO_5000C000_CLOCK_BUS
#define DT_SPI_1_BASE_ADDRESS \
DT_ST_STM32_SPI_FIFO_44004000_BASE_ADDRESS
#define DT_SPI_1_IRQ_PRI \
DT_ST_STM32_SPI_FIFO_44004000_IRQ_0_PRIORITY
#define DT_SPI_1_NAME \
DT_ST_STM32_SPI_FIFO_44004000_LABEL
#define DT_SPI_1_IRQ \
DT_ST_STM32_SPI_FIFO_44004000_IRQ_0
#define DT_SPI_1_CLOCK_BITS \
DT_ST_STM32_SPI_FIFO_44004000_CLOCK_BITS
#define DT_SPI_1_CLOCK_BUS \
DT_ST_STM32_SPI_FIFO_44004000_CLOCK_BUS
#define DT_SPI_2_BASE_ADDRESS \
DT_ST_STM32_SPI_FIFO_4400B000_BASE_ADDRESS
#define DT_SPI_2_IRQ_PRI \
DT_ST_STM32_SPI_FIFO_4400B000_IRQ_0_PRIORITY
#define DT_SPI_2_NAME \
DT_ST_STM32_SPI_FIFO_4400B000_LABEL
#define DT_SPI_2_IRQ \
DT_ST_STM32_SPI_FIFO_4400B000_IRQ_0
#define DT_SPI_2_CLOCK_BITS \
DT_ST_STM32_SPI_FIFO_4400B000_CLOCK_BITS
#define DT_SPI_2_CLOCK_BUS \
DT_ST_STM32_SPI_FIFO_4400B000_CLOCK_BUS
#define DT_SPI_3_BASE_ADDRESS \
DT_ST_STM32_SPI_FIFO_4400C000_BASE_ADDRESS
#define DT_SPI_3_IRQ_PRI \
DT_ST_STM32_SPI_FIFO_4400C000_IRQ_0_PRIORITY
#define DT_SPI_3_NAME \
DT_ST_STM32_SPI_FIFO_4400C000_LABEL
#define DT_SPI_3_IRQ \
DT_ST_STM32_SPI_FIFO_4400C000_IRQ_0
#define DT_SPI_3_CLOCK_BITS \
DT_ST_STM32_SPI_FIFO_4400C000_CLOCK_BITS
#define DT_SPI_3_CLOCK_BUS \
DT_ST_STM32_SPI_FIFO_4400C000_CLOCK_BUS
#define DT_SPI_4_BASE_ADDRESS \
DT_ST_STM32_SPI_FIFO_44005000_BASE_ADDRESS
#define DT_SPI_4_IRQ_PRI \
DT_ST_STM32_SPI_FIFO_44005000_IRQ_0_PRIORITY
#define DT_SPI_4_NAME \
DT_ST_STM32_SPI_FIFO_44005000_LABEL
#define DT_SPI_4_IRQ \
DT_ST_STM32_SPI_FIFO_44005000_IRQ_0
#define DT_SPI_4_CLOCK_BITS \
DT_ST_STM32_SPI_FIFO_44005000_CLOCK_BITS
#define DT_SPI_4_CLOCK_BUS \
DT_ST_STM32_SPI_FIFO_44005000_CLOCK_BUS
#define DT_SPI_5_BASE_ADDRESS \
DT_ST_STM32_SPI_FIFO_44009000_BASE_ADDRESS
#define DT_SPI_5_IRQ_PRI \
DT_ST_STM32_SPI_FIFO_44009000_IRQ_0_PRIORITY
#define DT_SPI_5_NAME \
DT_ST_STM32_SPI_FIFO_44009000_LABEL
#define DT_SPI_5_IRQ \
DT_ST_STM32_SPI_FIFO_44009000_IRQ_0
#define DT_SPI_5_CLOCK_BITS \
DT_ST_STM32_SPI_FIFO_44009000_CLOCK_BITS
#define DT_SPI_5_CLOCK_BUS \
DT_ST_STM32_SPI_FIFO_40009000_CLOCK_BUS
#define DT_UART_STM32_USART_2_BASE_ADDRESS \
DT_ST_STM32_USART_4000E000_BASE_ADDRESS
#define DT_UART_STM32_USART_2_BAUD_RATE \