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tests: test dynamic IRQ APIs

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The gen_isr_table test now tries to install two dynamic
IRQ handlers.

RISCV32 has a workaround due to limited number of SW
triggerable interrupts that can be configured.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit is contained in:
Andrew Boie 2018-11-12 11:37:52 -08:00 committed by Anas Nashif
parent e85986e153
commit 3aa59a6eed
2 changed files with 56 additions and 19 deletions
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2
tests/kernel/gen_isr_table/prj.conf
View file

@ -1,2 +1,2 @@
CONFIG_TEST=y
# Nothing needed
CONFIG_DYNAMIC_INTERRUPTS=y

73
tests/kernel/gen_isr_table/src/main.c
View file

@ -19,23 +19,29 @@ extern u32_t _irq_vector_table[];
#define ISR2_OFFSET 1
#if defined(CONFIG_RISCV32) && !defined(CONFIG_SOC_RISCV32_PULPINO)
/* RISC-V has very few IRQ lines which can be triggered from software */
#define ISR3_OFFSET 1
#define ISR4_OFFSET 5
#define ISR5_OFFSET 5
#define IRQ_LINE(offset) offset
#define TABLE_INDEX(offset) offset
#define TRIG_CHECK_SIZE 6
#define TRIG_CHECK_SIZE 6
#else
#define ISR3_OFFSET 2
#define ISR4_OFFSET 3
#define ISR5_OFFSET 4
#define ISR6_OFFSET 5
#define IRQ_LINE(offset) (CONFIG_NUM_IRQS - ((offset) + 1))
#define TABLE_INDEX(offset) (IRQ_TABLE_SIZE - ((offset) + 1))
#define TRIG_CHECK_SIZE 4
#define TRIG_CHECK_SIZE 6
#endif
#define ISR3_ARG 0xb01dface
#define ISR4_ARG 0xca55e77e
#define ISR5_ARG 0xf0ccac1a
#define ISR6_ARG 0xba5eba11
static volatile int trigger_check[TRIG_CHECK_SIZE];
#if defined(CONFIG_ARM)
@ -91,12 +97,27 @@ void isr3(void *param)
trigger_check[ISR3_OFFSET]++;
}
#ifdef ISR4_OFFSET
void isr4(void *param)
{
printk("%s ran with parameter %p\n", __func__, param);
trigger_check[ISR4_OFFSET]++;
}
#endif
void isr5(void *param)
{
printk("%s ran with parameter %p\n", __func__, param);
trigger_check[ISR5_OFFSET]++;
}
#ifdef ISR6_OFFSET
void isr6(void *param)
{
printk("%s ran with parameter %p\n", __func__, param);
trigger_check[ISR6_OFFSET]++;
}
#endif
#ifndef CONFIG_CPU_CORTEX_M
/* Need to turn optimization off. Otherwise compiler may generate incorrect
@ -209,7 +230,7 @@ static int check_sw_isr(void *isr, u32_t arg, int offset)
void main(void)
{
int rv;
int rv = TC_FAIL;
TC_START("Test gen_isr_tables");
@ -224,38 +245,54 @@ void main(void)
TC_PRINT("isr2 isr=%p irq=%d\n", isr2, IRQ_LINE(ISR2_OFFSET));
if (check_vector(isr1, ISR1_OFFSET)) {
rv = TC_FAIL;
goto done;
}
if (check_vector(isr2, ISR2_OFFSET)) {
rv = TC_FAIL;
goto done;
}
#endif
#ifdef CONFIG_GEN_SW_ISR_TABLE
IRQ_CONNECT(IRQ_LINE(ISR3_OFFSET), 1, isr3, ISR3_ARG, 0);
IRQ_CONNECT(IRQ_LINE(ISR4_OFFSET), 2, isr4, ISR4_ARG, 0);
irq_enable(IRQ_LINE(ISR3_OFFSET));
irq_enable(IRQ_LINE(ISR4_OFFSET));
TC_PRINT("isr3 isr=%p irq=%d param=%p\n", isr3, IRQ_LINE(ISR3_OFFSET),
(void *)ISR3_ARG);
TC_PRINT("isr4 isr=%p irq=%d param=%p\n", isr4, IRQ_LINE(ISR4_OFFSET),
(void *)ISR4_ARG);
TC_PRINT("_sw_isr_table at location %p\n", _sw_isr_table);
IRQ_CONNECT(IRQ_LINE(ISR3_OFFSET), 1, isr3, ISR3_ARG, 0);
irq_enable(IRQ_LINE(ISR3_OFFSET));
TC_PRINT("isr3 isr=%p irq=%d param=%p\n", isr3, IRQ_LINE(ISR3_OFFSET),
(void *)ISR3_ARG);
if (check_sw_isr(isr3, ISR3_ARG, ISR3_OFFSET)) {
rv = TC_FAIL;
goto done;
}
#ifdef ISR4_OFFSET
IRQ_CONNECT(IRQ_LINE(ISR4_OFFSET), 1, isr4, ISR4_ARG, 0);
irq_enable(IRQ_LINE(ISR4_OFFSET));
TC_PRINT("isr4 isr=%p irq=%d param=%p\n", isr4, IRQ_LINE(ISR4_OFFSET),
(void *)ISR4_ARG);
if (check_sw_isr(isr4, ISR4_ARG, ISR4_OFFSET)) {
rv = TC_FAIL;
goto done;
}
#endif
irq_connect_dynamic(IRQ_LINE(ISR5_OFFSET), 1, isr5, (void *)ISR5_ARG,
0);
irq_enable(IRQ_LINE(ISR5_OFFSET));
TC_PRINT("isr5 isr=%p irq=%d param=%p\n", isr5, IRQ_LINE(ISR5_OFFSET),
(void *)ISR5_ARG);
if (check_sw_isr(isr5, ISR5_ARG, ISR5_OFFSET)) {
goto done;
}
#ifdef ISR6_OFFSET
irq_connect_dynamic(IRQ_LINE(ISR6_OFFSET), 1, isr6, (void *)ISR6_ARG,
0);
irq_enable(IRQ_LINE(ISR6_OFFSET));
TC_PRINT("isr6 isr=%p irq=%d param=%p\n", isr6, IRQ_LINE(ISR6_OFFSET),
(void *)ISR6_ARG);
if (check_sw_isr(isr6, ISR6_ARG, ISR6_OFFSET)) {
goto done;
}
#endif
#endif /* CONFIG_GEN_SW_ISR_TABLE */
rv = TC_PASS;
done:
TC_END_RESULT(rv);