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drivers: clock_control: stm32f3: Enable PWR clock to access BDCR

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BDCR could be required for LSE or RTC for instance.
Enable it here as for now, no sophisticated PM handling is available
on F3 series.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2023-04-04 09:17:20 +02:00 committed by Carles Cufí
parent bd9bd38b87
commit 3abb0c9b4b
1 changed files with 3 additions and 0 deletions
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3
drivers/clock_control/clock_stm32f0_f3.c
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@ -150,6 +150,9 @@ void config_enable_default_clocks(void)
LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_SYSCFG);
#endif
#else
/* Enable PWR clock, required to access BDCR */
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
#if defined(CONFIG_USB_DC_STM32) && defined(SYSCFG_CFGR1_USB_IT_RMP)
/* Enable System Configuration Controller clock. */
/* SYSCFG is required to remap IRQ to avoid conflicts with CAN */