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soc: silabs_exx32: Add support for SiLabs EFR32MG21 SoC

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This commit adds support for Silicon Labs EFR32MG21 (Mighty Gecko) SoC.

Signed-off-by: Steven Lemaire <steven.lemaire@zii.aero>
This commit is contained in:
Steven Lemaire 2020-07-13 17:31:19 +02:00 committed by Carles Cufí
parent 97ec4a775e
commit 3ae6c67771
13 changed files with 423 additions and 3 deletions
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2
CODEOWNERS
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@ -41,6 +41,7 @@
/soc/arm/nordic_nrf/ @ioannisg
/soc/arm/nuvoton/ @ssekar15
/soc/arm/qemu_cortex_a53/ @carlocaione
/soc/arm/silabs_exx32/efr32mg21/ @l-alfred
/soc/arm/st_stm32/ @erwango
/soc/arm/st_stm32/stm32f4/ @idlethread
/soc/arm/st_stm32/stm32mp1/ @arnopo
@ -277,6 +278,7 @@
/dts/arm/silabs/efr32bg13p* @mnkp
/dts/arm/silabs/efm32jg12b* @chrta
/dts/arm/silabs/efm32pg12b* @chrta
/dts/arm/silabs/efr32mg21* @l-alfred
/dts/riscv/microsemi-miv.dtsi @galak
/dts/riscv/rv32m1* @MaureenHelm
/dts/riscv/riscv32-fe310.dtsi @nategraff-sifive

195
dts/arm/silabs/efr32mg21.dtsi Normal file
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@ -0,0 +1,195 @@
/*
* Copyright (c) 2020 TriaGnoSys GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv8-m.dtsi>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/i2c/i2c.h>
#include "gpio_gecko.h"
/ {
chosen {
zephyr,flash-controller = &msc;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m33f";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
mpu: mpu@e000ed90 {
compatible = "arm,armv8m-mpu";
reg = <0xe000ed90 0x40>;
arm,num-mpu-regions = <16>;
};
};
};
sram0: memory@20000000 {
device_type = "memory";
compatible = "mmio-sram";
};
soc {
msc: flash-controller@40030000 {
compatible = "silabs,gecko-flash-controller";
label = "FLASH_CTRL";
reg = <0x40030000 0x31a4>;
interrupts = <51 0>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@0 {
compatible = "soc-nv-flash";
label = "FLASH_0";
write-block-size = <4>;
erase-block-size = <8192>;
};
};
usart0: usart@40058000 { /* USART0 */
compatible = "silabs,gecko-usart";
reg = <0x40058000 0x400>;
interrupts = <11 0>, <12 0>;
interrupt-names = "rx", "tx";
peripheral-id = <0>;
status = "disabled";
label = "USART_0";
};
usart1: usart@4005c000 { /* USART1 */
compatible = "silabs,gecko-usart";
reg = <0x4005c000 0x400>;
interrupts = <13 0>, <14 0>;
interrupt-names = "rx", "tx";
peripheral-id = <1>;
status = "disabled";
label = "USART_1";
};
usart2: usart@40060000 { /* USART2 */
compatible = "silabs,gecko-usart";
reg = <0x40060000 0x400>;
interrupts = <15 0>, <16 0>;
interrupt-names = "rx", "tx";
peripheral-id = <2>;
status = "disabled";
label = "USART_2";
};
i2c0: i2c@4a010000 {
compatible = "silabs,gecko-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x4a010000 0x400>;
interrupts = <27 0>;
label = "I2C_0";
status = "disabled";
};
i2c1: i2c@40068000 {
compatible = "silabs,gecko-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40068000 0x400>;
interrupts = <28 0>;
label = "I2C_1";
status = "disabled";
};
rtcc0: rtcc@48000000 {
compatible = "silabs,gecko-rtcc";
reg = <0x48000000 0x400>;
interrupts = <10 0>;
clock-frequency = <32768>;
prescaler = <1>;
status = "disabled";
label = "RTCC_0";
};
gpio: gpio@4003c300 {
compatible = "silabs,gecko-gpio";
reg = <0x4003c300 0x3c00>;
interrupts = <26 2>, <25 2>;
interrupt-names = "GPIO_EVEN", "GPIO_ODD";
label = "GPIO";
ranges;
#address-cells = <1>;
#size-cells = <1>;
gpioa: gpio@4003c000 {
compatible = "silabs,gecko-gpio-port";
reg = <0x4003c000 0x30>;
peripheral-id = <0>;
label = "GPIO_A";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiob: gpio@4003c030 {
compatible = "silabs,gecko-gpio-port";
reg = <0x4003c030 0x30>;
peripheral-id = <1>;
label = "GPIO_B";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpioc: gpio@4003c060 {
compatible = "silabs,gecko-gpio-port";
reg = <0x4003c060 0x30>;
peripheral-id = <2>;
label = "GPIO_C";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiod: gpio@4003c090 {
compatible = "silabs,gecko-gpio-port";
reg = <0x4003c090 0x30>;
peripheral-id = <3>;
label = "GPIO_D";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
};
wdog0: wdog@4a018000 {
compatible = "silabs,gecko-wdog";
reg = <0x4a018000 0x2C>;
peripheral-id = <0>;
label = "WDOG0";
interrupts = <43 0>;
status = "disabled";
};
wdog1: wdog@4a01c000 {
compatible = "silabs,gecko-wdog";
reg = <0x4a01c000 0x2C>;
peripheral-id = <1>;
label = "WDOG1";
interrupts = <44 0>;
status = "disabled";
};
};
};
&nvic {
arm,num-irq-priority-bits = <4>;
};

24
dts/arm/silabs/efr32mg21a020f1024im32.dtsi Normal file
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@ -0,0 +1,24 @@
/*
* Copyright (c) 2019 Steven Lemaire
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <silabs/efr32mg21.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(96)>;
};
soc {
compatible = "silabs,efr32mg21a020f1024im32", "silabs,efr32mg21", "silabs,efr32", "simple-bus";
flash-controller@40030000 {
flash0: flash@0 {
reg = <0 DT_SIZE_K(1024)>;
};
};
};
};

5
soc/arm/silabs_exx32/Kconfig
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@ -81,6 +81,11 @@ config SOC_GECKO_RTCC
help
Set if the Real Time Counter and Calendar (RTCC) HAL module is used.
config SOC_GECKO_SE
bool
help
Set if the Secure Element (SE) HAL module is used.
config SOC_GECKO_TIMER
bool
help

55
soc/arm/silabs_exx32/common/soc.c
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@ -43,6 +43,28 @@ static const CMU_LFXOInit_TypeDef lfxoInit = CMU_LFXOINIT_DEFAULT;
static ALWAYS_INLINE void clock_init(void)
{
#ifdef CONFIG_CMU_HFCLK_HFXO
#if defined(_SILICON_LABS_32B_SERIES_2)
if (CMU_ClockSelectGet(cmuClock_SYSCLK) != cmuSelect_HFXO) {
/*
* Check if device has HFXO configuration info in DEVINFO
* See AN0016.2
*/
if ((DEVINFO->MODULEINFO & DEVINFO_MODULEINFO_HFXOCALVAL) ==
DEVINFO_MODULEINFO_HFXOCALVAL_VALID) {
hfxoInit.ctuneXoAna = (DEVINFO->MODXOCAL
& _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_MASK)
>> _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_SHIFT;
hfxoInit.ctuneXiAna = (DEVINFO->MODXOCAL
& _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK)
>> _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_SHIFT;
}
CMU_HFXOInit(&hfxoInit);
CMU_ClockSelectSet(cmuClock_SYSCLK, cmuSelect_HFXO);
}
SystemHFXOClockSet(CONFIG_CMU_HFXO_FREQ);
#else
if (CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_HFXO) {
CMU_HFXOInit(&hfxoInit);
CMU_OscillatorEnable(cmuOsc_HFXO, true, true);
@ -50,7 +72,25 @@ static ALWAYS_INLINE void clock_init(void)
}
SystemHFXOClockSet(CONFIG_CMU_HFXO_FREQ);
CMU_OscillatorEnable(cmuOsc_HFRCO, false, false);
#endif /* _SILICON_LABS_32B_SERIES_2 */
#elif (defined CONFIG_CMU_HFCLK_LFXO)
#if defined(_SILICON_LABS_32B_SERIES_2)
if (CMU_ClockSelectGet(cmuClock_SYSCLK) != cmuSelect_LFXO) {
/*
* Start the LFXO Oscillator as well (use by RTCC)
* Check if device has HFXO configuration info in DEVINFO
* See AN0016.2
*/
if ((DEVINFO->MODULEINFO & DEVINFO_MODULEINFO_LFXOCALVAL) ==
DEVINFO_MODULEINFO_LFXOCALVAL_VALID) {
lfxoInit.capTune = (DEVINFO->MODXOCAL
& _DEVINFO_MODXOCAL_LFXOCAPTUNE_MASK)
>> _DEVINFO_MODXOCAL_LFXOCAPTUNE_SHIFT;
}
}
SystemLFXOClockSet(CONFIG_CMU_LFXO_FREQ);
#else
if (CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_LFXO) {
CMU_LFXOInit(&lfxoInit);
CMU_OscillatorEnable(cmuOsc_LFXO, true, true);
@ -58,6 +98,7 @@ static ALWAYS_INLINE void clock_init(void)
}
SystemLFXOClockSet(CONFIG_CMU_LFXO_FREQ);
CMU_OscillatorEnable(cmuOsc_HFRCO, false, false);
#endif /* _SILICON_LABS_32B_SERIES_2 */
#elif (defined CONFIG_CMU_HFCLK_HFRCO)
/*
* This is the default clock, the controller starts with
@ -76,8 +117,13 @@ static ALWAYS_INLINE void clock_init(void)
#error "Unsupported clock source for HFCLK selected"
#endif
/* Enable the High Frequency Peripheral Clock */
CMU_ClockEnable(cmuClock_HFPER, true);
#if defined(_SILICON_LABS_32B_SERIES_2)
/* Enable the High Frequency Peripheral Clock */
CMU_ClockEnable(cmuClock_PCLK, true);
#else
/* Enable the High Frequency Peripheral Clock */
CMU_ClockEnable(cmuClock_HFPER, true);
#endif /* _SILICON_LABS_32B_SERIES_2 */
#if defined(CONFIG_GPIO_GECKO) || defined(CONFIG_LOG_BACKEND_SWO)
CMU_ClockEnable(cmuClock_GPIO, true);
@ -108,6 +154,9 @@ static void swo_init(void)
{
struct soc_gpio_pin pin_swo = PIN_SWO;
#if defined(_SILICON_LABS_32B_SERIES_2)
GPIO->TRACEROUTEPEN = GPIO_TRACEROUTEPEN_SWVPEN;
#else
/* Select HFCLK as the debug trace clock */
CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_HFCLK;
@ -120,6 +169,8 @@ static void swo_init(void)
#else
GPIO->ROUTE = GPIO_ROUTE_SWOPEN | (SWO_LOCATION << 8);
#endif
#endif /* _SILICON_LABS_32B_SERIES_2 */
soc_gpio_configure(&pin_swo);
}
#endif /* CONFIG_LOG_BACKEND_SWO */

20
soc/arm/silabs_exx32/efr32mg21/Kconfig.defconfig.efr32mg21 Normal file
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@ -0,0 +1,20 @@
# Silicon Labs EFR32MG21 (Mighty Gecko) MCU configuration options
# Copyright (c) 2020 TriaGnoSys GmbH
# SPDX-License-Identifier: Apache-2.0
config GPIO_GECKO
default y
depends on GPIO || LOG_BACKEND_SWO
config UART_GECKO
default y
depends on SERIAL
config I2C_GECKO
default y
depends on I2C
config SOC_FLASH_GECKO
default y
depends on FLASH

21
soc/arm/silabs_exx32/efr32mg21/Kconfig.defconfig.series Normal file
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@ -0,0 +1,21 @@
# Silicon Labs EFR32MG21 (Might Gecko) series configuration options
# Copyright (c) 2020 TriaGnoSys GmbH
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_EFR32MG21
config SOC_SERIES
default "efr32mg21"
config SOC_PART_NUMBER
default "EFR32MG21A020F1024IM32" if SOC_PART_NUMBER_EFR32MG21A020F1024IM32
config NUM_IRQS
int
# must be >= the highest interrupt number used
default 61
source "soc/arm/silabs_exx32/efr32mg21/Kconfig.defconfig.efr32mg21"
endif # SOC_SERIES_EFR32MG21

26
soc/arm/silabs_exx32/efr32mg21/Kconfig.series Normal file
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@ -0,0 +1,26 @@
# Silicon Labs EFR32MG21 (Mighty Gecko) MCU
# Copyright (c) 2020 TriaGnoSys GmbH
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_EFR32MG21
bool "EFR32MG21 Series MCU"
select ARM
select CPU_CORTEX_M33
select CPU_CORTEX_M_HAS_DWT
select ARMV8_M_DSP
select CPU_HAS_FPU
select CPU_HAS_ARM_MPU
select SOC_FAMILY_EXX32
select HAS_SILABS_GECKO
select HAS_SWO
select HAS_SYS_POWER_STATE_SLEEP_1
select HAS_SYS_POWER_STATE_SLEEP_2
select HAS_SYS_POWER_STATE_SLEEP_3
select SOC_GECKO_CORE
select SOC_GECKO_CMU
select SOC_GECKO_EMU
select SOC_GECKO_GPIO
select SOC_GECKO_SE
help
Enable support for EFR32MG21 Mighty Gecko MCU series

8
soc/arm/silabs_exx32/efr32mg21/Kconfig.soc Normal file
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@ -0,0 +1,8 @@
# Silicon Labs EFR32MG21 (Mighty Gecko) MCU line
# Copyright (c) 2020 TriaGnoSys GmbH
# SPDX-License-Identifier: Apache-2.0
config SOC_PART_NUMBER_EFR32MG21A020F1024IM32
bool
depends on SOC_SERIES_EFR32MG21

16
soc/arm/silabs_exx32/efr32mg21/linker.ld Normal file
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@ -0,0 +1,16 @@
/*
* Copyright (c) 2020 TriaGnoSys GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Linker command/script file
*
* This is the linker script for both standard images.
*/
#include <autoconf.h>
#include <arch/arm/aarch32/cortex_m/scripts/linker.ld>

30
soc/arm/silabs_exx32/efr32mg21/soc.h Normal file
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@ -0,0 +1,30 @@
/*
* Copyright (c) 2020 TriaGnoSys GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Board configuration macros for the EFR32MG21 SoC
*
*/
#ifndef ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG21_SOC_H
#define ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG21_SOC_H
#include <sys/util.h>
#ifndef _ASMLANGUAGE
#include <em_common.h>
#include "soc_pinmap.h"
#include "../common/soc_gpio.h"
/* Add include for DTS generated information */
#include <devicetree.h>
#endif /* !_ASMLANGUAGE */
#endif /* ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG21_SOC_H */

22
soc/arm/silabs_exx32/efr32mg21/soc_pinmap.h Normal file
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@ -0,0 +1,22 @@
/*
* Copyright (c) 2020 TriaGnoSys GmbH
* SPDX-License-Identifier: Apache-2.0
*/
/** @file
* @brief Silabs EFR32MG21 MCU pin definitions.
*
* This file contains pin configuration data required by different MCU
* modules to correctly configure GPIO controller.
*/
#ifndef ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG21_SOC_PINMAP_H_
#define ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG21_SOC_PINMAP_H_
#include <em_gpio.h>
#ifdef CONFIG_LOG_BACKEND_SWO
#define PIN_SWO { gpioPortA, 3, gpioModePushPull, 1 }
#endif /* CONFIG_LOG_BACKEND_SWO */
#endif /* ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG21_SOC_PINMAP_H_ */

2
west.yml
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@ -68,7 +68,7 @@ manifest:
revision: a1ec761014740a08699720298dd37ad4da360840
path: modules/hal/microchip
- name: hal_silabs
revision: 78da967feeac0d51219ef733cc3ccf643336589f
revision: 69c3e1e6e167767cb75aa2b468df4ade05988cdb
path: modules/hal/silabs
- name: hal_st
revision: 5b3ec3e182d4310e8943cc34c6c70ae57d9711da