nios2: set up common linker script for XIP and non-XIP
We will require 6 variables to be defined by SOC-specific linker script; these values in turn can be pulled from defines in layout.h. To help position code correctly we define two new ELF sections for this arch, 'reset' and 'exceptions'. Change-Id: Idffbd53895945b7d0ec0aac281e5bf7c85b4b2c2 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
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arch/nios2/soc/nios2e-zephyr/include/layout.h
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arch/nios2/soc/nios2e-zephyr/include/layout.h
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@ -0,0 +1,26 @@
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/*
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* Copyright (c) 2016 Intel Corporation
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <system.h>
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#define _RESET_VECTOR ALT_CPU_RESET_ADDR
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#define _EXC_VECTOR ALT_CPU_EXCEPTION_ADDR
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#define _ROM_ADDR ONCHIP_FLASH_0_DATA_BASE
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#define _ROM_SIZE ONCHIP_FLASH_0_DATA_SPAN
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#define _RAM_ADDR ONCHIP_MEMORY2_0_BASE
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#define _RAM_SIZE ONCHIP_MEMORY2_0_SPAN
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@ -18,4 +18,6 @@
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* @brief Linker script for the Nios II/e CPU with timer and 16550 UART
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*/
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#include <layout.h>
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#include <arch/nios2/linker.ld>
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@ -30,30 +30,76 @@
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#include <linker-defs.h>
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#include <linker-tool.h>
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#define ROMABLE_REGION FLASH
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#define RAMABLE_REGION SRAM
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/* These sections are specific to this CPU */
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#define _EXCEPTION_SECTION_NAME exceptions
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#define _RESET_SECTION_NAME reset
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#define ROM_ADDR CONFIG_FLASH_BASE_ADDRESS
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#define ROM_SIZE CONFIG_FLASH_SIZE * 1K
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/* This linker script requires the following macros to be defined in the
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* SOC-specfic linker script. All of these values can be found defined
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* in system.h for CPU configurations that can generate a HAL.
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*
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* _RESET_VECTOR CPU entry point at boot
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* _EXC_VECTOR General exception vector
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* _ROM_ADDR Beginning of flash memory
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* _ROM_SIZE Size in bytes of flash memory
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* _RAM_ADDR Beginning of RAM
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* _RAM_SIZE Size of RAM in bytes
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*
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* For now we support two scenarios:
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*
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* 1. Non-XIP systems where the reset vector is at the beginning of RAM
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* with the exception vector 0x20 bytes after it.
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* 2. XIP systems where the reset vector is at the beginning of ROM and
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* the exception vector is in RAM
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*/
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#define RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
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#define RAM_SIZE CONFIG_SRAM_SIZE * 1K
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#define _DATA_IN_ROM __data_rom_start
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#ifdef CONFIG_XIP
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#define ROMABLE_REGION FLASH
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#define RAMABLE_REGION SRAM
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#else
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#define ROMABLE_REGION SRAM
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#define RAMABLE_REGION SRAM
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#endif
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#ifdef CONFIG_XIP
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ASSERT(_RESET_VECTOR == _ROM_ADDR, "Reset vector not at beginning of ROM!")
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MEMORY
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{
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FLASH (rx) : ORIGIN = ROM_ADDR, LENGTH = ROM_SIZE
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SRAM (wx) : ORIGIN = RAM_ADDR, LENGTH = RAM_SIZE
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RESET (rx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20
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FLASH (rx) : ORIGIN = _RESET_VECTOR + 0x20 , LENGTH = (_ROM_SIZE - 0x20)
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SRAM (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)
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}
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#else
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ASSERT(_RESET_VECTOR == _RAM_ADDR, "Reset vector not at beginning of RAM!")
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ASSERT(_EXC_VECTOR - _RESET_VECTOR == 0x20, "Exception vector in wrong place?")
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MEMORY
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{
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RESET (wx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20
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SRAM (wx) : ORIGIN = _EXC_VECTOR, LENGTH = _RAM_SIZE - (_EXC_VECTOR - _RAM_ADDR)
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}
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#endif
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SECTIONS
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{
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GROUP_START(ROMABLE_REGION)
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_image_rom_start = CONFIG_FLASH_BASE_ADDRESS;
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_image_rom_start = _ROM_ADDR;
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SECTION_PROLOGUE(_RESET_SECTION_NAME,,)
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{
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*(.reset.*)
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} GROUP_LINK_IN(RESET)
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SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)
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{
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/* XXX If ALT_CPU_RESET_ADDR is not the same as _ROM_ADDR
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* we are going to waste flash space? */
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. = ALT_CPU_RESET_ADDR;
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_image_text_start = .;
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*(.text)
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_image_rom_end = .;
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__data_rom_start = ALIGN(4); /* XIP imaged DATA ROM start addr */
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GROUP_END(ROMABLE_REGION)
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GROUP_START(RAMABLE_REGION)
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_gp = ALIGN(16) + 0x7ff0;
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PROVIDE(gp = _gp);
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#ifdef CONFIG_XIP
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/* Altera strongly recommends keeping exception entry code in RAM
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* even on XIP systems
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*
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* XXX any space between _RAM_ADDR and ALT_CPU_EXCEPTION_ADDR is lost,
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* currently 0x20 bytes
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*
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* This is code not data, but we need this copied just like XIP data
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*/
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SECTION_AT_PROLOGUE(_DATA_SECTION_NAME,,,_DATA_IN_ROM)
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SECTION_AT_PROLOGUE(_EXCEPTION_SECTION_NAME,,, __data_rom_start)
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{
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_image_ram_start = .;
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__data_ram_start = .;
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/* FIXME these KEEP()s shouldn't be necessary */
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KEEP(*(".exception.entry.*"))
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KEEP(*(".exception.other.*"))
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} GROUP_LINK_IN(RAMABLE_REGION)
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#endif
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SECTION_PROLOGUE(_DATA_SECTION_NAME,,)
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{
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#ifndef CONFIG_XIP
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_image_ram_start = .;
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__data_ram_start = .;
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#endif
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*(.data)
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*(".data.*")
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} GROUP_LINK_IN(RAMABLE_REGION)
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} GROUP_LINK_IN(RAMABLE_REGION)
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/* Define linker symbols */
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_image_ram_end = .;
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_end = .; /* end of image */
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__bss_num_words = (__bss_end - __bss_start) >> 2;
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}
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#if CONFIG_XIP
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/*
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* Round up number of words for DATA section to ensure that XIP copies the
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* entire data section. XIP copy is done in words only, so there may be up
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*/
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__data_size = (__data_ram_end - __data_ram_start);
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__data_num_words = (__data_size + 3) >> 2;
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#endif
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@ -385,9 +385,10 @@ class SizeCalculator:
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alloc_sections = ["bss", "noinit"]
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rw_sections = ["datas", "initlevel", "_k_mem_map_ptr", "_k_pipe_ptr",
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"_k_task_ptr", "_k_task_list", "_k_event_list"]
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"_k_task_ptr", "_k_task_list", "_k_event_list",
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"exceptions"]
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# These get copied into RAM only on non-XIP
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ro_sections = ["text", "ctors", "init_array",
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ro_sections = ["text", "ctors", "init_array", "reset",
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"rodata", "devconfig", "gpio_compat"]
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def __init__(self, filename):
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