drivers: crypto: MEC172x crypto driver supporting hash
Implement zephyr crypto driver hash API's using calls to MEC172x ROM hash API's. Hardware supports zephyr driver hash modes: SHA-224, 256, 384, and 512. Driver supports synchronous (blocking) mode at this time. Signed-off-by: Manimaran A <manimaran.a@microchip.com>
This commit is contained in:
Manimaran A
Carles Cufí
parent
f8d9cd67c8
commit
3cc7d37b70
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@ -8,4 +8,5 @@ zephyr_library_sources_ifdef(CONFIG_CRYPTO_STM32 crypto_stm32.c)
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zephyr_library_sources_ifdef(CONFIG_CRYPTO_NRF_ECB crypto_nrf_ecb.c)
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zephyr_library_sources_ifdef(CONFIG_CRYPTO_INTEL_SHA crypto_intel_sha.c)
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zephyr_library_sources_ifdef(CONFIG_CRYPTO_NPCX_SHA crypto_npcx_sha.c)
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zephyr_library_sources_ifdef(CONFIG_CRYPTO_MCHP_XEC_SYMCR crypto_mchp_xec_symcr.c)
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zephyr_library_link_libraries_ifdef(CONFIG_MBEDTLS mbedTLS)
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@ -77,5 +77,6 @@ source "drivers/crypto/Kconfig.stm32"
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source "drivers/crypto/Kconfig.nrf_ecb"
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source "drivers/crypto/Kconfig.intel"
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source "drivers/crypto/Kconfig.npcx"
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source "drivers/crypto/Kconfig.xec"
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endif # CRYPTO
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12
drivers/crypto/Kconfig.xec
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12
drivers/crypto/Kconfig.xec
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@ -0,0 +1,12 @@
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# Copyright (c) 2022 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config CRYPTO_MCHP_XEC_SYMCR
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bool "Microchip XEC symmetric crypto (AES/Hash) driver"
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default y
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depends on DT_HAS_MICROCHIP_XEC_SYMCR_ENABLED
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help
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Enable Microchip XEC symmetic crypto (AES/Hash) driver.
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Symmetric crypto provides a single hardware interface
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to AES and hash engines.
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548
drivers/crypto/crypto_mchp_xec_symcr.c
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548
drivers/crypto/crypto_mchp_xec_symcr.c
Normal file
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@ -0,0 +1,548 @@
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/*
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* Copyright (c) 2023 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT microchip_xec_symcr
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#include <errno.h>
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#include <string.h>
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#include <zephyr/kernel.h>
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#include <zephyr/crypto/crypto.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/mchp_xec_clock_control.h>
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#include "zephyr/sys/util.h"
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(xec_symcr, CONFIG_CRYPTO_LOG_LEVEL);
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#include <soc.h>
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/* ROM API for Hash without using external files */
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enum mchp_rom_hash_alg_id {
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MCHP_ROM_HASH_ALG_NONE = 0,
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MCHP_ROM_HASH_ALG_SHA1,
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MCHP_ROM_HASH_ALG_SHA224,
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MCHP_ROM_HASH_ALG_SHA256,
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MCHP_ROM_HASH_ALG_SHA384,
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MCHP_ROM_HASH_ALG_SHA512,
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MCHP_ROM_HASH_ALG_SM3,
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MCHP_ROM_HASH_ALG_MAX
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};
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#define MCHP_XEC_STRUCT_HASH_STATE_STRUCT_SIZE 8
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#define MCHP_XEC_STRUCT_HASH_STRUCT_SIZE 240
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struct mchphashstate {
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uint32_t v[MCHP_XEC_STRUCT_HASH_STATE_STRUCT_SIZE / 4];
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};
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struct mchphash {
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uint32_t v[MCHP_XEC_STRUCT_HASH_STRUCT_SIZE / 4];
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};
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#define MCHP_XEC_ROM_API_BASE DT_REG_ADDR(DT_NODELABEL(rom_api))
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#define MCHP_XEC_ROM_API_ADDR(n) \
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(((uint32_t)(MCHP_XEC_ROM_API_BASE) + ((uint32_t)(n) * 4u)) | BIT(0))
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#define MCHP_XEC_ROM_HASH_CREATE_SHA224_ID 95
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#define mchp_xec_rom_hash_create_sha224 \
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((int (*)(struct mchphash *)) MCHP_XEC_ROM_API_ADDR(MCHP_XEC_ROM_HASH_CREATE_SHA224_ID))
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#define MCHP_XEC_ROM_HASH_CREATE_SHA256_ID 96
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#define mchp_xec_rom_hash_create_sha256 \
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((int (*)(struct mchphash *)) MCHP_XEC_ROM_API_ADDR(MCHP_XEC_ROM_HASH_CREATE_SHA256_ID))
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#define MCHP_XEC_ROM_HASH_CREATE_SHA384_ID 97
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#define mchp_xec_rom_hash_create_sha384 \
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((int (*)(struct mchphash *)) MCHP_XEC_ROM_API_ADDR(MCHP_XEC_ROM_HASH_CREATE_SHA384_ID))
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#define MCHP_XEC_ROM_HASH_CREATE_SHA512_ID 98
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#define mchp_xec_rom_hash_create_sha512 \
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((int (*)(struct mchphash *)) MCHP_XEC_ROM_API_ADDR(MCHP_XEC_ROM_HASH_CREATE_SHA512_ID))
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#define MCHP_XEC_ROM_HASH_INIT_STATE_ID 100
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#define mec172x_rom_hash_init_state \
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((void (*)(struct mchphash *, struct mchphashstate *, char *)) \
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MCHP_XEC_ROM_API_ADDR(MCHP_XEC_ROM_HASH_INIT_STATE_ID))
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#define MCHP_XEC_ROM_HASH_RESUME_STATE_ID 101
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#define mchp_xec_rom_hash_resume_state \
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((void (*)(struct mchphash *, struct mchphashstate *)) \
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MCHP_XEC_ROM_API_ADDR(MCHP_XEC_ROM_HASH_RESUME_STATE_ID))
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#define MCHP_XEC_ROM_HASH_SAVE_STATE_ID 102
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#define mchp_xec_rom_hash_save_state \
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((int (*)(struct mchphash *)) MCHP_XEC_ROM_API_ADDR(MCHP_XEC_ROM_HASH_SAVE_STATE_ID))
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#define MCHP_XEC_ROM_HASH_FEED_ID 103
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#define mchp_xec_rom_hash_feed \
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((int (*)(struct mchphash *, const uint8_t *, size_t)) \
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MCHP_XEC_ROM_API_ADDR(MCHP_XEC_ROM_HASH_FEED_ID))
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#define MCHP_XEC_ROM_HASH_DIGEST_ID 104
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#define mchp_xec_rom_hash_digest \
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((int (*)(struct mchphash *, char *)) MCHP_XEC_ROM_API_ADDR(MCHP_XEC_ROM_HASH_DIGEST_ID))
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#define MCHP_XEC_ROM_HASH_WAIT_ID 105
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#define mec172x_rom_hash_wait \
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((int (*)(struct mchphash *)) MCHP_XEC_ROM_API_ADDR(MCHP_XEC_ROM_HASH_WAIT_ID))
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#define MCHP_XEC_ROM_AH_DMA_INIT_ID 144
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#define mchp_xec_rom_ah_dma_init \
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((int (*)(uint8_t)) MCHP_XEC_ROM_API_ADDR(MCHP_XEC_ROM_AH_DMA_INIT_ID))
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#define MCHP_ROM_AH_DMA_INIT_NO_RESET 0
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#define MCHP_ROM_AH_DMA_INIT_WITH_RESET 1
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#define MCHP_XEC_SYMCR_CAPS_SUPPORT \
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(CAP_RAW_KEY | CAP_SEPARATE_IO_BUFS | CAP_SYNC_OPS | CAP_NO_IV_PREFIX)
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#define MCHP_XEC_SYMCR_MAX_SESSION 1
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#define MCHP_XEC_STATE_BUF_SIZE 256
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#define MCHP_XEC_BLOCK_BUF_SIZE 128
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struct xec_symcr_hash_session {
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struct mchphash mhctx;
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struct mchphashstate mhstate;
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enum hash_algo algo;
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enum mchp_rom_hash_alg_id rom_algo;
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bool open;
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size_t blksz;
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size_t blklen;
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uint8_t blockbuf[MCHP_XEC_BLOCK_BUF_SIZE] __aligned(4);
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uint8_t statebuf[MCHP_XEC_STATE_BUF_SIZE] __aligned(4);
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};
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struct xec_symcr_config {
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uint32_t regbase;
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const struct device *clk_dev;
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struct mchp_xec_pcr_clk_ctrl clk_ctrl;
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uint8_t irq_num;
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uint8_t girq;
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uint8_t girq_pos;
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uint8_t rsvd1;
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};
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struct xec_symcr_data {
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struct xec_symcr_hash_session hash_sessions[MCHP_XEC_SYMCR_MAX_SESSION];
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};
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static int mchp_xec_get_unused_session_index(struct xec_symcr_data *data)
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{
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int i;
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for (i = 0; i < MCHP_XEC_SYMCR_MAX_SESSION; i++) {
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if (!data->hash_sessions[i].open) {
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data->hash_sessions[i].open = true;
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return i;
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}
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}
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return -EPERM;
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}
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struct hash_alg_to_rom {
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enum hash_algo algo;
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enum mchp_rom_hash_alg_id rom_algo;
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};
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const struct hash_alg_to_rom hash_alg_tbl[] = {
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{ CRYPTO_HASH_ALGO_SHA224, MCHP_ROM_HASH_ALG_SHA224 },
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{ CRYPTO_HASH_ALGO_SHA256, MCHP_ROM_HASH_ALG_SHA256 },
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{ CRYPTO_HASH_ALGO_SHA384, MCHP_ROM_HASH_ALG_SHA384 },
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{ CRYPTO_HASH_ALGO_SHA512, MCHP_ROM_HASH_ALG_SHA512 },
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};
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static enum mchp_rom_hash_alg_id lookup_hash_alg(enum hash_algo algo)
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{
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for (size_t n = 0; n < ARRAY_SIZE(hash_alg_tbl); n++) {
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if (hash_alg_tbl[n].algo == algo) {
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return hash_alg_tbl[n].rom_algo;
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}
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}
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return MCHP_ROM_HASH_ALG_NONE;
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}
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/* SHA-1, 224, and 256 use block size of 64 bytes
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* SHA-384 and 512 use 128 bytes.
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*/
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static size_t hash_block_size(enum hash_algo algo)
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{
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switch (algo) {
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case CRYPTO_HASH_ALGO_SHA384:
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case CRYPTO_HASH_ALGO_SHA512:
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return 128u;
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default:
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return 64u;
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}
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}
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static int init_rom_hash_context(enum mchp_rom_hash_alg_id rom_algo, struct mchphash *c)
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{
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int ret = 0;
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if (!c) {
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return -EINVAL;
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}
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switch (rom_algo) {
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case MCHP_ROM_HASH_ALG_SHA224:
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ret = mchp_xec_rom_hash_create_sha224(c);
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break;
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case MCHP_ROM_HASH_ALG_SHA256:
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ret = mchp_xec_rom_hash_create_sha256(c);
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break;
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case MCHP_ROM_HASH_ALG_SHA384:
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ret = mchp_xec_rom_hash_create_sha384(c);
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break;
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case MCHP_ROM_HASH_ALG_SHA512:
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ret = mchp_xec_rom_hash_create_sha512(c);
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break;
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default:
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return -EINVAL;
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}
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if (ret) { /* use zephyr return value */
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ret = -EIO;
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}
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return ret;
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}
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/* use zephyr return values */
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int mchp_xec_rom_hash_init_state_wrapper(struct mchphash *c, struct mchphashstate *h,
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uint8_t *dmamem)
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{
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if (!c || !h || !dmamem) {
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return -EINVAL;
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}
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mec172x_rom_hash_init_state(c, h, (char *)dmamem);
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return 0;
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}
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int mchp_xec_rom_hash_resume_state_wrapper(struct mchphash *c, struct mchphashstate *h)
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{
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if (!c || !h) {
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return -EINVAL;
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}
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mchp_xec_rom_hash_resume_state(c, h);
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return 0;
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}
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int mchp_xec_rom_hash_save_state_wrapper(struct mchphash *c)
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{
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if (!c) {
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return -EINVAL;
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}
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if (mchp_xec_rom_hash_save_state(c) != 0) {
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return -EIO;
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}
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return 0;
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}
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int mchp_xec_rom_hash_feed_wrapper(struct mchphash *c, const uint8_t *msg, size_t sz)
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{
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if ((!c) || (!msg && sz)) {
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return -EINVAL;
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}
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if (mchp_xec_rom_hash_feed(c, (const char *)msg, sz) != 0) {
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return -EIO;
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}
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return 0;
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}
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int mchp_xec_rom_hash_digest_wrapper(struct mchphash *c, uint8_t *digest)
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{
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if (!c || !digest) {
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return -EINVAL;
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}
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if (mchp_xec_rom_hash_digest(c, (char *)digest)) {
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return -EIO;
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}
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return 0;
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}
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/* Wait for hardware to finish.
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* returns 0 if hardware finished with no errors
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* returns -EIO if hardware stopped due to error
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* returns -EINVAL if parameter is bad, hardware may still be running!
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*/
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int mchp_xec_rom_hash_wait_wrapper(struct mchphash *c)
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{
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if (!c) {
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return -EINVAL;
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}
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if (mec172x_rom_hash_wait(c) != 0) {
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return -EIO;
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}
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return 0;
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}
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/* Called by application for update(finish==false)
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* and compute final hash digest(finish==true)
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*/
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static int xec_symcr_do_hash(struct hash_ctx *ctx, struct hash_pkt *pkt, bool finish)
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{
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struct xec_symcr_hash_session *hs = NULL;
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struct mchphash *c = NULL;
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struct mchphashstate *cstate = NULL;
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size_t fill_len = 0, rem_len = 0;
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int ret = 0;
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if (!ctx || !pkt) {
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return -EINVAL;
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}
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hs = (struct xec_symcr_hash_session *)ctx->drv_sessn_state;
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c = &hs->mhctx;
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cstate = &hs->mhstate;
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if (!hs->open) {
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LOG_ERR("Session not open");
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return -EIO;
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}
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if (!finish && !pkt->in_len) {
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return 0; /* nothing to do */
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}
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/* Not final digest computation and not enough data to run engine */
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if (!finish && ((hs->blklen + pkt->in_len) < hs->blksz)) {
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memcpy(&hs->blockbuf[hs->blklen], pkt->in_buf, pkt->in_len);
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hs->blklen += pkt->in_len;
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return 0;
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}
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ret = init_rom_hash_context(hs->rom_algo, c);
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if (ret) {
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LOG_ERR("ROM context init error %d", ret);
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return ret;
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}
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ret = mchp_xec_rom_hash_resume_state_wrapper(c, cstate);
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if (ret) {
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LOG_ERR("Resume state error %d", ret);
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return ret;
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}
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fill_len = pkt->in_len;
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rem_len = 0;
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if (!finish) {
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rem_len = pkt->in_len & (hs->blksz - 1u);
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fill_len = pkt->in_len & ~(hs->blksz - 1u);
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if (hs->blklen) {
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fill_len = ((hs->blklen + pkt->in_len) & ~(hs->blksz - 1u)) - hs->blklen;
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rem_len = pkt->in_len - fill_len;
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}
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}
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if (hs->blklen) {
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ret = mchp_xec_rom_hash_feed_wrapper(c, (const uint8_t *)hs->blockbuf, hs->blklen);
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if (ret) {
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LOG_ERR("ROM hash feed error %d", ret);
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return ret;
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}
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hs->blklen = 0; /* consumed */
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}
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ret = mchp_xec_rom_hash_feed_wrapper(c, (const uint8_t *)pkt->in_buf, fill_len);
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if (ret) {
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LOG_ERR("ROM hash feed error %d", ret);
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return ret;
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}
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if (finish) {
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ret = mchp_xec_rom_hash_digest_wrapper(c, pkt->out_buf);
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if (ret) {
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LOG_ERR("ROM Hash final error %d", ret);
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return ret;
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}
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} else {
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ret = mchp_xec_rom_hash_save_state(c);
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if (ret) {
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LOG_ERR("ROM hash save state error %d", ret);
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return ret;
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}
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}
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ret = mchp_xec_rom_hash_wait_wrapper(c);
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if (ret) {
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LOG_ERR("ROM hash wait error %d", ret);
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return ret;
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}
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if (finish) {
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hs->blklen = 0;
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} else {
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memcpy(hs->blockbuf, &pkt->in_buf[fill_len], rem_len);
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hs->blklen = rem_len;
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}
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return 0;
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}
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||||
static int xec_symcr_hash_session_begin(const struct device *dev, struct hash_ctx *ctx,
|
||||
enum hash_algo algo)
|
||||
{
|
||||
struct xec_symcr_data *data = dev->data;
|
||||
struct xec_symcr_hash_session *hs = NULL;
|
||||
struct mchphash *c = NULL;
|
||||
struct mchphashstate *cstate = NULL;
|
||||
enum mchp_rom_hash_alg_id rom_algo = MCHP_ROM_HASH_ALG_NONE;
|
||||
int session_idx = 0;
|
||||
int ret = 0;
|
||||
|
||||
if (ctx->flags & ~(MCHP_XEC_SYMCR_CAPS_SUPPORT)) {
|
||||
LOG_ERR("Unsupported flag");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
rom_algo = lookup_hash_alg(algo);
|
||||
if (rom_algo == MCHP_ROM_HASH_ALG_NONE) {
|
||||
LOG_ERR("Unsupported algo %d", algo);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
session_idx = mchp_xec_get_unused_session_index(data);
|
||||
if (session_idx < 0) {
|
||||
LOG_ERR("No session available");
|
||||
return -ENOSPC;
|
||||
}
|
||||
|
||||
hs = &data->hash_sessions[session_idx];
|
||||
|
||||
hs->algo = algo;
|
||||
hs->rom_algo = rom_algo;
|
||||
hs->open = false;
|
||||
hs->blklen = 0;
|
||||
hs->blksz = hash_block_size(algo);
|
||||
|
||||
ctx->drv_sessn_state = hs;
|
||||
ctx->started = false;
|
||||
ctx->hash_hndlr = xec_symcr_do_hash;
|
||||
|
||||
/* reset HW at beginning of session */
|
||||
ret = mchp_xec_rom_ah_dma_init(MCHP_ROM_AH_DMA_INIT_WITH_RESET);
|
||||
if (ret) {
|
||||
LOG_ERR("ROM HW init error %d", ret);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
c = &hs->mhctx;
|
||||
cstate = &hs->mhstate;
|
||||
|
||||
ret = init_rom_hash_context(hs->rom_algo, c);
|
||||
if (ret) {
|
||||
LOG_ERR("ROM HW context init error %d", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = mchp_xec_rom_hash_init_state_wrapper(c, cstate, hs->statebuf);
|
||||
if (ret) {
|
||||
LOG_ERR("ROM HW init state error %d", ret);
|
||||
}
|
||||
|
||||
hs->open = true;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* struct hash_ctx {
|
||||
* const struct device *device; this device driver's instance structure
|
||||
* void *drv_sessn_state; pointer to driver instance struct session state. Defined by driver
|
||||
* hash_op hash_hndlr; pointer to this driver function. App calls via pointer to do operations
|
||||
* bool started; true if multipart hash has been started
|
||||
* uint16_t flags; app populates this before calling hash_begin_session
|
||||
* }
|
||||
*/
|
||||
static int xec_symcr_hash_session_free(const struct device *dev, struct hash_ctx *ctx)
|
||||
{
|
||||
struct xec_symcr_hash_session *hs = NULL;
|
||||
int ret = 0;
|
||||
|
||||
ret = mchp_xec_rom_ah_dma_init(MCHP_ROM_AH_DMA_INIT_WITH_RESET);
|
||||
if (ret) {
|
||||
ret = -EIO;
|
||||
LOG_ERR("ROM HW reset error %d", ret);
|
||||
}
|
||||
|
||||
hs = (struct xec_symcr_hash_session *)ctx->drv_sessn_state;
|
||||
|
||||
memset(hs, 0, sizeof(struct xec_symcr_hash_session));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int xec_symcr_query_hw_caps(const struct device *dev)
|
||||
{
|
||||
return MCHP_XEC_SYMCR_CAPS_SUPPORT;
|
||||
}
|
||||
|
||||
static int xec_symcr_init(const struct device *dev)
|
||||
{
|
||||
const struct xec_symcr_config *cfg = dev->config;
|
||||
int ret;
|
||||
|
||||
if (!device_is_ready(cfg->clk_dev)) {
|
||||
LOG_ERR("clock device not ready");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
ret = clock_control_on(cfg->clk_dev, (clock_control_subsys_t *)&cfg->clk_ctrl);
|
||||
if (ret < 0) {
|
||||
LOG_ERR("clock on error %d", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = mchp_xec_rom_ah_dma_init(MCHP_ROM_AH_DMA_INIT_WITH_RESET);
|
||||
if (ret) {
|
||||
ret = -EIO;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct crypto_driver_api xec_symcr_api = {
|
||||
.query_hw_caps = xec_symcr_query_hw_caps,
|
||||
.hash_begin_session = xec_symcr_hash_session_begin,
|
||||
.hash_free_session = xec_symcr_hash_session_free,
|
||||
};
|
||||
|
||||
#define XEC_SYMCR_PCR_INFO(i) \
|
||||
MCHP_XEC_PCR_SCR_ENCODE(DT_INST_CLOCKS_CELL(i, regidx), \
|
||||
DT_INST_CLOCKS_CELL(i, bitpos), \
|
||||
DT_INST_CLOCKS_CELL(i, domain))
|
||||
|
||||
#define XEC_SYMCR_INIT(inst) \
|
||||
\
|
||||
static struct xec_symcr_data xec_symcr_data_##inst; \
|
||||
\
|
||||
static const struct xec_symcr_config xec_symcr_cfg_##inst = { \
|
||||
.regbase = DT_INST_REG_ADDR(inst), \
|
||||
.clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)), \
|
||||
.clk_ctrl = { \
|
||||
.pcr_info = XEC_SYMCR_PCR_INFO(inst), \
|
||||
}, \
|
||||
.irq_num = DT_INST_IRQN(inst), \
|
||||
.girq = DT_INST_PROP_BY_IDX(inst, girqs, 0), \
|
||||
.girq_pos = DT_INST_PROP_BY_IDX(inst, girqs, 1), \
|
||||
}; \
|
||||
\
|
||||
DEVICE_DT_INST_DEFINE(inst, &xec_symcr_init, NULL, \
|
||||
&xec_symcr_data_##inst, &xec_symcr_cfg_##inst, \
|
||||
POST_KERNEL, CONFIG_CRYPTO_INIT_PRIORITY, \
|
||||
&xec_symcr_api);
|
||||
|
||||
DT_INST_FOREACH_STATUS_OKAY(XEC_SYMCR_INIT)
|
||||
|
|
@ -471,10 +471,10 @@
|
|||
dmac: dmac@40002400 {
|
||||
compatible = "microchip,xec-dmac";
|
||||
reg = <0x40002400 0xc00>;
|
||||
interrupts = <24 0>, <25 0>, <26 0>, <27 0>,
|
||||
<28 0>, <29 0>, <30 0>, <31 0>,
|
||||
<32 0>, <33 0>, <34 0>, <35 0>,
|
||||
<36 0>, <37 0>, <38 0>, <39 0>;
|
||||
interrupts = <24 1>, <25 1>, <26 1>, <27 1>,
|
||||
<28 1>, <29 1>, <30 1>, <31 1>,
|
||||
<32 1>, <33 1>, <34 1>, <35 1>,
|
||||
<36 1>, <37 1>, <38 1>, <39 1>;
|
||||
girqs = < MCHP_XEC_ECIA(14, 0, 6, 24)
|
||||
MCHP_XEC_ECIA(14, 1, 6, 25)
|
||||
MCHP_XEC_ECIA(14, 2, 6, 26)
|
||||
|
|
@ -1027,6 +1027,22 @@
|
|||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
symcr: symcr@40100000 {
|
||||
compatible = "microchip,xec-symcr";
|
||||
reg = <0x40100000 0x1000>;
|
||||
interrupts = <68 1>;
|
||||
clocks = <&pcr 3 26 MCHP_XEC_PCR_CLK_PERIPH>;
|
||||
girqs = <16 3>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
rom_api: rom_api@1f000 {
|
||||
reg = <0x1f000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
20
dts/bindings/crypto/microchip,xec-symcr.yaml
Normal file
20
dts/bindings/crypto/microchip,xec-symcr.yaml
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
# Copyright (c) 2023 Microchip Technology Inc.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Microchip XEC symmetric crypto (AES/Hash) accelerator.
|
||||
|
||||
compatible: "microchip,xec-symcr"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
clocks:
|
||||
required: true
|
||||
|
||||
girqs:
|
||||
type: array
|
||||
required: true
|
||||
description: XEC ECIA GIRQ number and bit position.
|
||||
Loading…
Reference in a new issue