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driver: adc: infineon: Adding ADC driver

Browse source 
- This includes the driver, test app, and sample app
- Only the boards\arm\cy8cproto_062_4343w board is supported for now

Signed-off-by: Bill Waters <bill.waters@infineon.com>
This commit is contained in:
Bill Waters 2023-04-06 12:53:39 -07:00 committed by Marti Bolivar
parent c410ebe5fe
commit 3e02d48e4e
12 changed files with 465 additions and 13 deletions
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1
boards/arm/cy8cproto_062_4343w/cy8cproto_062_4343w.yaml
View file

@ -13,6 +13,7 @@ toolchain:
- zephyr
- gnuarmemb
supported:
- adc
- gpio
- uart
- i2c

3
drivers/adc/CMakeLists.txt
View file

@ -8,7 +8,7 @@ zephyr_library_sources_ifdef(CONFIG_ADC_ITE_IT8XXX2 adc_ite_it8xxx2.c)
zephyr_library_sources_ifdef(CONFIG_ADC_SHELL adc_shell.c)
zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_ADC12 adc_mcux_adc12.c)
zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_ADC16 adc_mcux_adc16.c)
zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_12B1MSPS_SAR adc_mcux_12b1msps_sar.c)
zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_12B1MSPS_SAR adc_mcux_12b1msps_sar.c)
zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_LPADC adc_mcux_lpadc.c)
zephyr_library_sources_ifdef(CONFIG_ADC_SAM_AFEC adc_sam_afec.c)
zephyr_library_sources_ifdef(CONFIG_ADC_NRFX_ADC adc_nrfx_adc.c)
@ -33,3 +33,4 @@ zephyr_library_sources_ifdef(CONFIG_ADC_RPI_PICO adc_rpi_pico.c)
zephyr_library_sources_ifdef(CONFIG_ADC_XMC4XXX adc_xmc4xxx.c)
zephyr_library_sources_ifdef(CONFIG_ADC_ESP32 adc_esp32.c)
zephyr_library_sources_ifdef(CONFIG_ADC_GECKO iadc_gecko.c)
zephyr_library_sources_ifdef(CONFIG_ADC_INFINEON_CAT1 adc_ifx_cat1.c)

2
drivers/adc/Kconfig
View file

@ -92,4 +92,6 @@ source "drivers/adc/Kconfig.xmc4xxx"
source "drivers/adc/Kconfig.gecko"
source "drivers/adc/Kconfig.ifx_cat1"
endif # ADC

15
drivers/adc/Kconfig.ifx_cat1 Normal file
View file

@ -0,0 +1,15 @@
# Infineon CAT1 ADC configuration options
# Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
#
# SPDX-License-Identifier: Apache-2.0
config ADC_INFINEON_CAT1
bool "Infineon CAT1 ADC driver"
default y
depends on DT_HAS_INFINEON_CAT1_ADC_ENABLED
select USE_INFINEON_ADC
select ADC_CONFIGURABLE_INPUTS
help
This option enables the ADC driver for Infineon CAT1 family.

296
drivers/adc/adc_ifx_cat1.c Normal file
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@ -0,0 +1,296 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief ADC driver for Infineon CAT1 MCU family.
*/
#define DT_DRV_COMPAT infineon_cat1_adc
#include <zephyr/drivers/adc.h>
#include <cyhal_adc.h>
#include <cyhal_utils_psoc.h>
#define ADC_CONTEXT_USES_KERNEL_TIMER
#include "adc_context.h"
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(ifx_cat1_adc, CONFIG_ADC_LOG_LEVEL);
#if defined(PASS_SARMUX_PADS0_PORT)
#define _ADCSAR_PORT PASS_SARMUX_PADS0_PORT
#else
#error The selected device does not supported ADC
#endif
#define ADC_CAT1_EVENTS_MASK (CYHAL_ADC_EOS | CYHAL_ADC_ASYNC_READ_COMPLETE)
#define ADC_CAT1_DEFAULT_ACQUISITION_NS (1000u)
#define ADC_CAT1_RESOLUTION (12u)
#define ADC_CAT1_REF_INTERNAL_MV (1200u)
struct ifx_cat1_adc_data {
struct adc_context ctx;
const struct device *dev;
cyhal_adc_t adc_obj;
cyhal_adc_channel_t adc_chan_obj[CY_SAR_SEQ_NUM_CHANNELS];
uint16_t *buffer;
uint16_t *repeat_buffer;
uint32_t channels;
uint32_t channels_mask;
};
struct ifx_cat1_adc_config {
uint8_t irq_priority;
};
static void _cyhal_adc_event_callback(void *callback_arg, cyhal_adc_event_t event)
{
const struct device *dev = (const struct device *) callback_arg;
struct ifx_cat1_adc_data *data = dev->data;
uint32_t channels = data->channels;
int32_t result;
uint32_t channel_id;
while (channels != 0) {
channel_id = find_lsb_set(channels) - 1;
channels &= ~BIT(channel_id);
result = Cy_SAR_GetResult32(data->adc_chan_obj[channel_id].adc->base,
data->adc_chan_obj[channel_id].channel_idx);
/* Legacy API for BWC. Convert from signed to unsigned by adding 0x800 to
* convert the lowest signed 12-bit number to 0x0.
*/
*data->buffer = (uint16_t)(result + 0x800);
data->buffer++;
}
adc_context_on_sampling_done(&data->ctx, dev);
LOG_DBG("%s ISR triggered.", dev->name);
}
static void adc_context_start_sampling(struct adc_context *ctx)
{
struct ifx_cat1_adc_data *data = CONTAINER_OF(ctx, struct ifx_cat1_adc_data, ctx);
data->repeat_buffer = data->buffer;
Cy_SAR_StartConvert(data->adc_obj.base, CY_SAR_START_CONVERT_SINGLE_SHOT);
}
static void adc_context_update_buffer_pointer(struct adc_context *ctx,
bool repeat_sampling)
{
struct ifx_cat1_adc_data *data = CONTAINER_OF(ctx, struct ifx_cat1_adc_data, ctx);
if (repeat_sampling) {
data->buffer = data->repeat_buffer;
}
}
static int ifx_cat1_adc_channel_setup(const struct device *dev,
const struct adc_channel_cfg *channel_cfg)
{
struct ifx_cat1_adc_data *data = dev->data;
cy_rslt_t result;
cyhal_gpio_t vplus = CYHAL_GET_GPIO(_ADCSAR_PORT, channel_cfg->input_positive);
cyhal_gpio_t vminus = channel_cfg->differential ?
CYHAL_GET_GPIO(_ADCSAR_PORT, channel_cfg->input_negative) :
CYHAL_ADC_VNEG;
uint32_t acquisition_ns = ADC_CAT1_DEFAULT_ACQUISITION_NS;
if (channel_cfg->reference != ADC_REF_INTERNAL) {
LOG_ERR("Selected ADC reference is not valid");
return -EINVAL;
}
if (channel_cfg->gain != ADC_GAIN_1) {
LOG_ERR("Selected ADC gain is not valid");
return -EINVAL;
}
if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
switch (ADC_ACQ_TIME_UNIT(channel_cfg->acquisition_time)) {
case ADC_ACQ_TIME_MICROSECONDS:
acquisition_ns = ADC_ACQ_TIME_VALUE(channel_cfg->acquisition_time) * 1000;
break;
case ADC_ACQ_TIME_NANOSECONDS:
acquisition_ns = ADC_ACQ_TIME_VALUE(channel_cfg->acquisition_time);
break;
default:
LOG_ERR("Selected ADC acquisition time units is not valid");
return -EINVAL;
}
}
/* ADC channel configuration */
const cyhal_adc_channel_config_t channel_config = {
/* Disable averaging for channel */
.enable_averaging = false,
/* Minimum acquisition time set to 1us */
.min_acquisition_ns = acquisition_ns,
/* Sample channel when ADC performs a scan */
.enabled = true
};
/* Initialize a channel and configure it to scan the input pin(s). */
cyhal_adc_channel_free(&data->adc_chan_obj[channel_cfg->channel_id]);
result = cyhal_adc_channel_init_diff(&data->adc_chan_obj[channel_cfg->channel_id],
&data->adc_obj, vplus, vminus, &channel_config);
if (result != CY_RSLT_SUCCESS) {
LOG_ERR("ADC channel initialization failed. Error: 0x%08X\n", (unsigned int)result);
return -EIO;
}
data->channels_mask |= BIT(channel_cfg->channel_id);
return 0;
}
static int validate_buffer_size(const struct adc_sequence *sequence)
{
int active_channels = 0;
int total_buffer_size;
for (int i = 0; i < CY_SAR_SEQ_NUM_CHANNELS; i++) {
if (sequence->channels & BIT(i)) {
active_channels++;
}
}
total_buffer_size = active_channels * sizeof(uint16_t);
if (sequence->options) {
total_buffer_size *= (1 + sequence->options->extra_samplings);
}
if (sequence->buffer_size < total_buffer_size) {
return -ENOMEM;
}
return 0;
}
static int start_read(const struct device *dev,
const struct adc_sequence *sequence)
{
struct ifx_cat1_adc_data *data = dev->data;
uint32_t channels = sequence->channels;
uint32_t unconfigured_channels = channels & ~data->channels_mask;
if (sequence->resolution != ADC_CAT1_RESOLUTION) {
LOG_ERR("Invalid ADC resolution (%d)", sequence->resolution);
return -EINVAL;
}
if (unconfigured_channels != 0) {
LOG_ERR("ADC channel(s) not configured: 0x%08X\n", unconfigured_channels);
return -EINVAL;
}
if (sequence->oversampling) {
LOG_ERR("Oversampling not supported");
return -ENOTSUP;
}
int return_val = validate_buffer_size(sequence);
if (return_val < 0) {
LOG_ERR("Invalid sequence buffer size");
return return_val;
}
data->channels = channels;
data->buffer = sequence->buffer;
adc_context_start_read(&data->ctx, sequence);
return adc_context_wait_for_completion(&data->ctx);
}
static int ifx_cat1_adc_read(const struct device *dev,
const struct adc_sequence *sequence)
{
int ret;
struct ifx_cat1_adc_data *data = dev->data;
adc_context_lock(&data->ctx, false, NULL);
ret = start_read(dev, sequence);
adc_context_release(&data->ctx, ret);
return ret;
}
#ifdef CONFIG_ADC_ASYNC
static int ifx_cat1_adc_read_async(const struct device *dev,
const struct adc_sequence *sequence,
struct k_poll_signal *async)
{
int ret;
struct ifx_cat1_adc_data *data = dev->data;
adc_context_lock(&data->ctx, true, async);
ret = start_read(dev, sequence);
adc_context_release(&data->ctx, ret);
return ret;
}
#endif
static int ifx_cat1_adc_init(const struct device *dev)
{
struct ifx_cat1_adc_data *data = dev->data;
const struct ifx_cat1_adc_config *config = dev->config;
cy_rslt_t result;
data->dev = dev;
/* Initialize ADC. The ADC block which can connect to the input pin is selected */
result = cyhal_adc_init(&data->adc_obj, CYHAL_GET_GPIO(_ADCSAR_PORT, 0), NULL);
if (result != CY_RSLT_SUCCESS) {
LOG_ERR("ADC initialization failed. Error: 0x%08X\n", (unsigned int)result);
return -EIO;
}
/* Enable ADC Interrupt */
cyhal_adc_enable_event(&data->adc_obj, (cyhal_adc_event_t)ADC_CAT1_EVENTS_MASK,
config->irq_priority, true);
cyhal_adc_register_callback(&data->adc_obj, _cyhal_adc_event_callback, (void *) dev);
adc_context_unlock_unconditionally(&data->ctx);
return 0;
}
static const struct adc_driver_api adc_cat1_driver_api = {
.channel_setup = ifx_cat1_adc_channel_setup,
.read = ifx_cat1_adc_read,
#ifdef CONFIG_ADC_ASYNC
.read_async = ifx_cat1_adc_read_async,
#endif
.ref_internal = ADC_CAT1_REF_INTERNAL_MV
};
/* Macros for ADC instance declaration */
#define INFINEON_CAT1_ADC_INIT(n) \
static struct ifx_cat1_adc_data ifx_cat1_adc_data##n = { \
ADC_CONTEXT_INIT_TIMER(ifx_cat1_adc_data##n, ctx), \
ADC_CONTEXT_INIT_LOCK(ifx_cat1_adc_data##n, ctx), \
ADC_CONTEXT_INIT_SYNC(ifx_cat1_adc_data##n, ctx), \
}; \
\
static const struct ifx_cat1_adc_config adc_cat1_cfg_##n = { \
.irq_priority = DT_INST_IRQ(n, priority), \
}; \
\
DEVICE_DT_INST_DEFINE(n, ifx_cat1_adc_init, \
NULL, &ifx_cat1_adc_data##n, \
&adc_cat1_cfg_##n, \
POST_KERNEL, CONFIG_ADC_INIT_PRIORITY, \
&adc_cat1_driver_api);
DT_INST_FOREACH_STATUS_OKAY(INFINEON_CAT1_ADC_INIT)

7
dts/arm/infineon/psoc6/psoc6_02/psoc6_02.dtsi
View file

@ -113,6 +113,13 @@
interrupts = <50 6>;
status = "disabled";
};
adc0: adc@409d0000 {
compatible = "infineon,cat1-adc";
reg = <0x409d0000 0x10000>;
interrupts = <155 6>;
status = "disabled";
#io-channel-cells = <1>;
};
uart0: uart@40600000 {
compatible = "infineon,cat1-uart";
reg = <0x40600000 0x10000>;

28
dts/bindings/adc/infineon,cat1-adc.yaml Normal file
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@ -0,0 +1,28 @@
# Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
#
# SPDX-License-Identifier: Apache-2.0
description: |
Infineon Cat1 ADC
Each ADC group Cat1 is assigned to a Zephyr device. Refer to the Infineon PSoC6 reference
manual (Section Port I/O functions) for the group/chanel mapping to a specific port-pin on
the board. For example on the cy8cproto_062_4343w P10.0 is mapped to adc0,channel0 and
P10.1 is mapped to adc0,channel1.
compatible: "infineon,cat1-adc"
include: adc-controller.yaml
properties:
reg:
required: true
interrupts:
required: true
"#io-channel-cells":
const: 1
io-channel-cells:
- input

1
modules/hal_infineon/CMakeLists.txt
View file

@ -4,6 +4,7 @@
if(CONFIG_HAS_XMCLIB OR CONFIG_SOC_FAMILY_PSOC6 OR CONFIG_SOC_FAMILY_INFINEON_CAT1)
zephyr_library_named(modules_hal_infineon)
zephyr_library_compile_options(-Wno-array-bounds)
endif()
## Add PDL sources for XMC devices

16
modules/hal_infineon/mtb-hal-cat1/CMakeLists.txt
View file

@ -1,4 +1,5 @@
# Copyright (c) 2022 Cypress Semiconductor Corporation.
# Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
#
# SPDX-License-Identifier: Apache-2.0
@ -67,19 +68,22 @@ zephyr_library_sources_ifdef(CONFIG_SOC_DIE_PSOC6_04
# High level interface for interacting with CAT1 hardware
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_ADC ${hal_psoc6_dir}/source/cyhal_adc_sar.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_UART ${hal_psoc6_dir}/source/cyhal_uart.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_I2C ${hal_psoc6_dir}/source/cyhal_i2c.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_LPTIMER ${hal_psoc6_dir}/source/cyhal_lptimer.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_PWM ${hal_psoc6_dir}/source/cyhal_pwm.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_RTC ${hal_psoc6_dir}/source/cyhal_rtc.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_SDIO ${hal_psoc6_dir}/source/cyhal_sdhc.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_SPI ${hal_psoc6_dir}/source/cyhal_spi.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_TIMER ${hal_psoc6_dir}/source/cyhal_timer.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_PWM ${hal_psoc6_dir}/source/cyhal_pwm.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_LPTIMER ${hal_psoc6_dir}/source/cyhal_lptimer.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_RTC ${hal_psoc6_dir}/source/cyhal_rtc.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_TRNG ${hal_psoc6_dir}/source/cyhal_trng.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_SDIO ${hal_psoc6_dir}/source/cyhal_sdhc.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_UART ${hal_psoc6_dir}/source/cyhal_uart.c)
if(CONFIG_USE_INFINEON_ADC)
zephyr_library_sources(${hal_psoc6_dir}/source/cyhal_analog_common.c)
zephyr_library_sources(${hal_psoc6_dir}/source/cyhal_dma.c)
zephyr_library_sources(${hal_psoc6_dir}/source/cyhal_dma_dmac.c)
zephyr_library_sources(${hal_psoc6_dir}/source/cyhal_dma_dw.c)
endif()
if(CONFIG_USE_INFINEON_TIMER)

15
modules/hal_infineon/mtb-pdl-cat1/CMakeLists.txt
View file

@ -1,4 +1,5 @@
# Copyright (c) 2022 Cypress Semiconductor Corporation.
# Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
#
# SPDX-License-Identifier: Apache-2.0
@ -24,16 +25,16 @@ zephyr_library_sources_ifdef(CONFIG_CPU_CORTEX_M0PLUS
${pdl_dev_cat1a_dir}/templates/COMPONENT_MTB/COMPONENT_CM0P/system_psoc6_cm0plus.c)
# Peripheral drivers
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_UART ${pdl_drv_dir}/source/cy_scb_uart.c)
zephyr_library_sources_ifdef(CONFIG_SOC_FAMILY_PSOC6 ${pdl_drv_dir}/source/cy_sysint.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_ADC ${pdl_drv_dir}/source/cy_sar.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_I2C ${pdl_drv_dir}/source/cy_scb_i2c.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_SPI ${pdl_drv_dir}/source/cy_scb_spi.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_TIMER ${pdl_drv_dir}/source/cy_tcpwm_counter.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_PWM ${pdl_drv_dir}/source/cy_tcpwm_pwm.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_LPTIMER ${pdl_drv_dir}/source/cy_mcwdt.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_PWM ${pdl_drv_dir}/source/cy_tcpwm_pwm.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_RTC ${pdl_drv_dir}/source/cy_rtc.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_SDIO ${pdl_drv_dir}/source/cy_sd_host.c)
zephyr_library_sources_ifdef(CONFIG_SOC_FAMILY_PSOC6 ${pdl_drv_dir}/source/cy_sysint.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_SPI ${pdl_drv_dir}/source/cy_scb_spi.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_TIMER ${pdl_drv_dir}/source/cy_tcpwm_counter.c)
zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_UART ${pdl_drv_dir}/source/cy_scb_uart.c)
if(CONFIG_USE_INFINEON_TRNG)
zephyr_library_sources(${pdl_drv_dir}/source/cy_crypto.c)
@ -46,6 +47,8 @@ if(CONFIG_USE_INFINEON_UART OR CONFIG_USE_INFINEON_I2C OR CONFIG_USE_INFINEON_SP
endif()
if(CONFIG_USE_INFINEON_ADC)
zephyr_library_sources(${pdl_drv_dir}/source/cy_dma.c)
zephyr_library_sources(${pdl_drv_dir}/source/cy_dmac.c)
zephyr_library_sources(${pdl_drv_dir}/source/cy_sysanalog.c)
endif()

56
samples/drivers/adc/boards/cy8cproto_062_4343w.overlay Normal file
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@ -0,0 +1,56 @@
/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*/
#include <zephyr/dt-bindings/adc/adc.h>
/ {
zephyr,user {
io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>;
};
};
&adc0 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 1)>;
zephyr,gain = "ADC_GAIN_1";
zephyr,reference = "ADC_REF_INTERNAL";
zephyr,resolution = <12>;
zephyr,input-positive = <0>; /* P10.0 */
};
channel@1 {
reg = <1>;
zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 1)>;
zephyr,gain = "ADC_GAIN_1";
zephyr,reference = "ADC_REF_INTERNAL";
zephyr,resolution = <12>;
zephyr,input-positive = <1>; /* P10.1 */
};
channel@2 {
reg = <2>;
zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 1)>;
zephyr,gain = "ADC_GAIN_1";
zephyr,reference = "ADC_REF_INTERNAL";
zephyr,resolution = <12>;
zephyr,input-positive = <2>; /* P10.2 */
};
channel@3 {
reg = <3>;
zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 1)>;
zephyr,gain = "ADC_GAIN_1";
zephyr,reference = "ADC_REF_INTERNAL";
zephyr,resolution = <12>;
zephyr,input-positive = <3>; /* P10.3 */
};
};

38
tests/drivers/adc/adc_api/boards/cy8cproto_062_4343w.overlay Normal file
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@ -0,0 +1,38 @@
/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*/
#include <zephyr/dt-bindings/adc/adc.h>
/ {
zephyr,user {
io-channels = <&adc0 0>, <&adc0 1>;
};
};
&adc0 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
reg = <0>;
zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 1)>;
zephyr,gain = "ADC_GAIN_1";
zephyr,reference = "ADC_REF_INTERNAL";
zephyr,resolution = <12>;
zephyr,input-positive = <0>; /* P10.0 */
};
channel@1 {
reg = <1>;
zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 1)>;
zephyr,gain = "ADC_GAIN_1";
zephyr,reference = "ADC_REF_INTERNAL";
zephyr,resolution = <12>;
zephyr,input-positive = <1>; /* P10.1 */
};
};