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arch: arm: aarch32: Rearrange exception stack frame

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Cortex-A/R use a descending stack frame and the hardware does not help
with the stacking.  This led to some less than desirable workarounds in
the exception code where the basic stack frame was saved twice.
Rearranging the order of the exception stack frame removes that problem
and provides a clearer path to saving CPU context in a fully descending
manner.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
This commit is contained in:
Bradley Bolen 2022-04-04 15:41:12 -04:00 committed by Stephanos Ioannidis
parent 18398948db
commit 3f7162fc07
2 changed files with 43 additions and 31 deletions
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47
arch/arm/core/aarch32/cortex_a_r/exc.S
View file

@ -47,49 +47,34 @@ GTEXT(z_arm_data_abort)
stmfd sp, {r0-r3, r12, lr}^
sub sp, #24
/*
* Create new esf struct for exception handler debug. The first
* time the basic stack frame is saved is for getting in and out
* of the exception.
*/
#if defined(CONFIG_EXTRA_EXCEPTION_INFO)
sub sp, #___callee_saved_t_SIZEOF
sub sp, #___extra_esf_info_t_SIZEOF
#endif
srsdb sp!, #\mode
stmfd sp, {r0-r3, r12, lr}^
sub sp, #24
/* Increment exception nesting count */
ldr r2, =_kernel
ldr r0, [r2, #_kernel_offset_to_nested]
add r0, r0, #1
str r0, [r2, #_kernel_offset_to_nested]
#if defined(CONFIG_EXTRA_EXCEPTION_INFO)
/* Pointer to extra esf info */
add r0, sp, #___basic_sf_t_SIZEOF
mov r1, #0
str r1, [r0, #4]
str r1, [r0, #8]
/* Pointer to callee saved registers */
add r1, r0, #___extra_esf_info_t_SIZEOF
str r1, [r0]
sub sp, #___extra_esf_info_t_SIZEOF
mov r0, #0
str r0, [sp, #4]
str r0, [sp, #8]
sub r1, sp, #___callee_saved_t_SIZEOF
str r1, [sp]
cps #MODE_SYS
stm r1, {r4-r11, sp}
cps #\mode
mov r0, sp
mov sp, r1
#else
mov r0, sp
#endif
/* Invoke fault handler */
mov r0, sp
/* Increment exception nesting count */
ldr r2, =_kernel
ldr r1, [r2, #_kernel_offset_to_nested]
add r1, r1, #1
str r1, [r2, #_kernel_offset_to_nested]
.endm
.macro exception_exit
/* Exit exception */
add sp, sp, #___basic_sf_t_SIZEOF
#if defined(CONFIG_EXTRA_EXCEPTION_INFO)
add sp, #___extra_esf_info_t_SIZEOF
add sp, #___callee_saved_t_SIZEOF

27
include/zephyr/arch/arm/aarch32/exc.h
View file

@ -83,6 +83,8 @@ struct __extra_esf_info {
};
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
#if defined(CONFIG_CPU_CORTEX_M)
struct __esf {
struct __basic_sf {
sys_define_gpr_with_alias(a1, r0);
@ -104,6 +106,31 @@ struct __esf {
#endif
};
#else
struct __esf {
#if defined(CONFIG_EXTRA_EXCEPTION_INFO)
struct __extra_esf_info extra_info;
#endif
#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
float s[16];
uint32_t fpscr;
uint32_t undefined;
#endif
struct __basic_sf {
sys_define_gpr_with_alias(a1, r0);
sys_define_gpr_with_alias(a2, r1);
sys_define_gpr_with_alias(a3, r2);
sys_define_gpr_with_alias(a4, r3);
sys_define_gpr_with_alias(ip, r12);
sys_define_gpr_with_alias(lr, r14);
sys_define_gpr_with_alias(pc, r15);
uint32_t xpsr;
} basic;
};
#endif
extern uint32_t z_arm_coredump_fault_sp;
typedef struct __esf z_arch_esf_t;