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arch: introduce arch_secondary_cpu_init

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Different architecture are doing this in custom ways and using different
naming conventions, unify this interface and make it part of the arch
implementation for SMP.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2023-12-13 15:27:41 -05:00 committed by Carles Cufí
parent 2f3b7fa9bf
commit 3f75373584
8 changed files with 13 additions and 13 deletions
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2
arch/arc/core/reset.S
View file

@ -174,7 +174,7 @@ _slave_core_wait:
jl z_arc_firq_stack_set
pop r0
#endif
j z_arc_slave_start
j arch_secondary_cpu_init
_master_core_startup:
#endif

2
arch/arc/core/smp.c
View file

@ -89,7 +89,7 @@ static void arc_connect_debug_mask_update(int cpu_num)
void arc_core_private_intc_init(void);
/* the C entry of slave cores */
void z_arc_slave_start(int cpu_num)
void arch_secondary_cpu_init(int cpu_num)
{
arch_cpustart_t fn;

2
arch/arm/core/cortex_a_r/reset.S
View file

@ -217,7 +217,7 @@ EL1_Reset_Handler:
bne 1b
/* we can now move on */
ldr r4, =z_arm_secondary_start
ldr r4, =arch_secondary_cpu_init
ldr r5, [r0, #BOOT_PARAM_FIQ_SP_OFFSET]
ldr r6, [r0, #BOOT_PARAM_IRQ_SP_OFFSET]
ldr r7, [r0, #BOOT_PARAM_ABT_SP_OFFSET]

4
arch/arm/core/cortex_a_r/smp.c
View file

@ -148,7 +148,7 @@ void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz, arch_cpustart_
* \todo Support PSCI
*/
/* Wait secondary cores up, see z_arm64_secondary_start */
/* Wait secondary cores up, see arch_secondary_cpu_init */
while (arm_cpu_boot_params.fn) {
wfe();
}
@ -159,7 +159,7 @@ void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz, arch_cpustart_
}
/* the C entry of secondary cores */
void z_arm_secondary_start(void)
void arch_secondary_cpu_init(void)
{
int cpu_num = arm_cpu_boot_params.cpu_num;
arch_cpustart_t fn;

4
arch/arm64/core/prep_c.c
View file

@ -71,10 +71,10 @@ void z_prep_c(void)
#if CONFIG_MP_MAX_NUM_CPUS > 1
extern FUNC_NORETURN void z_arm64_secondary_start(void);
extern FUNC_NORETURN void arch_secondary_cpu_init(void);
void z_arm64_secondary_prep_c(void)
{
z_arm64_secondary_start();
arch_secondary_cpu_init();
CODE_UNREACHABLE;
}

6
arch/arm64/core/smp.c
View file

@ -122,7 +122,7 @@ void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
k_panic();
}
/* Wait secondary cores up, see z_arm64_secondary_start */
/* Wait secondary cores up, see arch_secondary_cpu_init */
while (arm64_cpu_boot_params.fn) {
wfe();
}
@ -133,9 +133,9 @@ void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
}
/* the C entry of secondary cores */
void z_arm64_secondary_start(void)
void arch_secondary_cpu_init(int cpu_num)
{
int cpu_num = arm64_cpu_boot_params.cpu_num;
cpu_num = arm64_cpu_boot_params.cpu_num;
arch_cpustart_t fn;
void *arg;

4
arch/riscv/core/reset.S
View file

@ -19,7 +19,7 @@ GTEXT(__reset)
GTEXT(z_prep_c)
GTEXT(riscv_cpu_wake_flag)
GTEXT(riscv_cpu_sp)
GTEXT(z_riscv_secondary_cpu_init)
GTEXT(arch_secondary_cpu_init)
#if CONFIG_INCLUDE_RESET_VECTOR
SECTION_FUNC(reset, __reset)
@ -111,7 +111,7 @@ wait_secondary_wake_flag:
la t0, riscv_cpu_boot_flag
li t1, 1
sr t1, 0(t0)
j z_riscv_secondary_cpu_init
j arch_secondary_cpu_init
#else
j loop_unconfigured_cores
#endif

2
arch/riscv/core/smp.c
View file

@ -43,7 +43,7 @@ void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
}
}
void z_riscv_secondary_cpu_init(int hartid)
void arch_secondary_cpu_init(int hartid)
{
unsigned int i;
unsigned int cpu_num = 0;