drivers: timer: stm32 adjust lptimer with slow LPTIM clock
Commit to adjust the next_arr with slow LPTIM clock The next_arr must not be < 0. Signed-off-by: Francois Ramu <francois.ramu@st.com>
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@ -61,10 +61,10 @@ static const struct device *const clk_ctrl = DEVICE_DT_GET(STM32_CLOCK_CONTROL_N
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* 0xFFFF / (LSE freq (32768Hz) / 128)
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*/
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static uint32_t lptim_clock_freq = 32000;
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static uint32_t lptim_clock_freq = KHZ(32);
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static int32_t lptim_time_base;
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/* The prescaler given by the DTS and to apply to the lptim clock */
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/* The prescaler given by the DTS and to apply to the lptim_clock_freq */
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#define LPTIM_CLOCK_RATIO DT_PROP(DT_DRV_INST(0), st_prescaler)
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/* Minimum nb of clock cycles to have to set autoreload register correctly */
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@ -225,9 +225,9 @@ void sys_clock_set_timeout(int32_t ticks, bool idle)
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next_arr = (((lp_time * CONFIG_SYS_CLOCK_TICKS_PER_SEC)
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/ lptim_clock_freq) + 1) * lptim_clock_freq
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/ (CONFIG_SYS_CLOCK_TICKS_PER_SEC);
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/* add count unit from the expected nb of Ticks */
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next_arr = next_arr + ((uint32_t)(ticks) * lptim_clock_freq)
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/ CONFIG_SYS_CLOCK_TICKS_PER_SEC - 1;
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/ CONFIG_SYS_CLOCK_TICKS_PER_SEC;
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/* if the lptim_clock_freq < one ticks/sec, then next_arr must be > 0 */
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/* maximise to TIMEBASE */
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if (next_arr > lptim_time_base) {
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@ -240,6 +240,8 @@ void sys_clock_set_timeout(int32_t ticks, bool idle)
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else if (next_arr < (lp_time + LPTIM_GUARD_VALUE)) {
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next_arr = lp_time + LPTIM_GUARD_VALUE;
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}
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/* with slow lptim_clock_freq, LPTIM_GUARD_VALUE of 1 is enough */
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next_arr = next_arr - 1;
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/* Update autoreload register */
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lptim_set_autoreload(next_arr);
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