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dts: Introduce 'resets' property to STM32 UART nodes

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We are about to add UART reset during driver initialization. First step
is to add 'resets' property, which provides information about reset
register offset and bit.

Signed-off-by: Patryk Duda <pdk@semihalf.com>
This commit is contained in:
Patryk Duda 2022-12-07 12:48:01 +01:00 committed by Marti Bolivar
parent 227ac76828
commit 4555c1a695
41 changed files with 132 additions and 1 deletions
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2
dts/arm/st/f0/stm32f0.dtsi
View file

@ -159,6 +159,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
resets = <&rctl STM32_RESET(APB2, 14U)>;
interrupts = <27 0>;
status = "disabled";
};
@ -167,6 +168,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
resets = <&rctl STM32_RESET(APB1, 17U)>;
interrupts = <28 0>;
status = "disabled";
};

4
dts/arm/st/f0/stm32f030Xc.dtsi
View file

@ -39,6 +39,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
resets = <&rctl STM32_RESET(APB1, 18U)>;
interrupts = <29 0>;
status = "disabled";
};
@ -47,6 +48,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
resets = <&rctl STM32_RESET(APB1, 19U)>;
interrupts = <29 0>;
status = "disabled";
};
@ -55,6 +57,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
resets = <&rctl STM32_RESET(APB1, 20U)>;
interrupts = <29 0>;
status = "disabled";
};
@ -63,6 +66,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
resets = <&rctl STM32_RESET(APB2, 5U)>;
interrupts = <29 0>;
status = "disabled";
};

3
dts/arm/st/f1/stm32f1.dtsi
View file

@ -159,6 +159,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
resets = <&rctl STM32_RESET(APB2, 14U)>;
interrupts = <37 0>;
status = "disabled";
};
@ -167,6 +168,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
resets = <&rctl STM32_RESET(APB1, 17U)>;
interrupts = <38 0>;
status = "disabled";
};
@ -175,6 +177,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
resets = <&rctl STM32_RESET(APB1, 18U)>;
interrupts = <39 0>;
status = "disabled";
};

2
dts/arm/st/f1/stm32f103Xc.dtsi
View file

@ -27,6 +27,7 @@
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
resets = <&rctl STM32_RESET(APB1, 19U)>;
interrupts = <52 0>;
status = "disabled";
};
@ -35,6 +36,7 @@
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
resets = <&rctl STM32_RESET(APB1, 20U)>;
interrupts = <53 0>;
status = "disabled";
};

2
dts/arm/st/f1/stm32f105.dtsi
View file

@ -66,6 +66,7 @@
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
resets = <&rctl STM32_RESET(APB1, 19U)>;
interrupts = <52 0>;
status = "disabled";
};
@ -74,6 +75,7 @@
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
resets = <&rctl STM32_RESET(APB1, 20U)>;
interrupts = <53 0>;
status = "disabled";
};

6
dts/arm/st/f2/stm32f2.dtsi
View file

@ -219,6 +219,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000010>;
resets = <&rctl STM32_RESET(APB2, 4U)>;
interrupts = <37 0>;
status = "disabled";
};
@ -227,6 +228,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
resets = <&rctl STM32_RESET(APB1, 17U)>;
interrupts = <38 0>;
status = "disabled";
};
@ -235,6 +237,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
resets = <&rctl STM32_RESET(APB1, 18U)>;
interrupts = <39 0>;
status = "disabled";
};
@ -243,6 +246,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
resets = <&rctl STM32_RESET(APB2, 5U)>;
interrupts = <71 0>;
status = "disabled";
};
@ -251,6 +255,7 @@
compatible ="st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
resets = <&rctl STM32_RESET(APB1, 19U)>;
interrupts = <52 0>;
status = "disabled";
};
@ -259,6 +264,7 @@
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
resets = <&rctl STM32_RESET(APB1, 20U)>;
interrupts = <53 0>;
status = "disabled";
};

4
dts/arm/st/f3/stm32f3.dtsi
View file

@ -175,6 +175,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
resets = <&rctl STM32_RESET(APB2, 14U)>;
interrupts = <37 0>;
status = "disabled";
};
@ -183,6 +184,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
resets = <&rctl STM32_RESET(APB1, 17U)>;
interrupts = <38 0>;
status = "disabled";
};
@ -191,6 +193,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
resets = <&rctl STM32_RESET(APB1, 18U)>;
interrupts = <39 0>;
status = "disabled";
};
@ -199,6 +202,7 @@
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
resets = <&rctl STM32_RESET(APB1, 19U)>;
interrupts = <52 0>;
status = "disabled";
};

1
dts/arm/st/f3/stm32f303.dtsi
View file

@ -49,6 +49,7 @@
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
resets = <&rctl STM32_RESET(APB1, 20U)>;
interrupts = <53 0>;
status = "disabled";
};

3
dts/arm/st/f4/stm32f4.dtsi
View file

@ -196,6 +196,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000010>;
resets = <&rctl STM32_RESET(APB2, 4U)>;
interrupts = <37 0>;
status = "disabled";
};
@ -204,6 +205,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
resets = <&rctl STM32_RESET(APB1, 17U)>;
interrupts = <38 0>;
status = "disabled";
};
@ -212,6 +214,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
resets = <&rctl STM32_RESET(APB2, 5U)>;
interrupts = <71 0>;
status = "disabled";
};

3
dts/arm/st/f4/stm32f405.dtsi
View file

@ -45,6 +45,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
resets = <&rctl STM32_RESET(APB1, 18U)>;
interrupts = <39 0>;
status = "disabled";
};
@ -53,6 +54,7 @@
compatible ="st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
resets = <&rctl STM32_RESET(APB1, 19U)>;
interrupts = <52 0>;
status = "disabled";
};
@ -61,6 +63,7 @@
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
resets = <&rctl STM32_RESET(APB1, 20U)>;
interrupts = <53 0>;
status = "disabled";
};

1
dts/arm/st/f4/stm32f412.dtsi
View file

@ -36,6 +36,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
resets = <&rctl STM32_RESET(APB1, 18U)>;
interrupts = <39 0>;
status = "disabled";
};

6
dts/arm/st/f4/stm32f413.dtsi
View file

@ -12,6 +12,7 @@
compatible ="st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
resets = <&rctl STM32_RESET(APB1, 19U)>;
interrupts = <52 0>;
status = "disabled";
};
@ -20,6 +21,7 @@
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
resets = <&rctl STM32_RESET(APB1, 20U)>;
interrupts = <53 0>;
status = "disabled";
};
@ -28,6 +30,7 @@
compatible = "st,stm32-uart";
reg = <0x40007800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
resets = <&rctl STM32_RESET(APB1, 30U)>;
interrupts = <82 0>;
status = "disabled";
};
@ -36,6 +39,7 @@
compatible = "st,stm32-uart";
reg = <0x40007c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
resets = <&rctl STM32_RESET(APB1, 31U)>;
interrupts = <83 0>;
status = "disabled";
};
@ -44,6 +48,7 @@
compatible = "st,stm32-uart";
reg = <0x40011800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000040>;
resets = <&rctl STM32_RESET(APB2, 6U)>;
interrupts = <88 0>;
status = "disabled";
};
@ -52,6 +57,7 @@
compatible = "st,stm32-uart";
reg = <0x40011c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
resets = <&rctl STM32_RESET(APB2, 7U)>;
interrupts = <89 0>;
status = "disabled";
};

2
dts/arm/st/f4/stm32f427.dtsi
View file

@ -33,6 +33,7 @@
compatible = "st,stm32-uart";
reg = <0x40007800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
resets = <&rctl STM32_RESET(APB1, 30U)>;
interrupts = <82 0>;
status = "disabled";
};
@ -41,6 +42,7 @@
compatible = "st,stm32-uart";
reg = <0x40007c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
resets = <&rctl STM32_RESET(APB1, 31U)>;
interrupts = <83 0>;
status = "disabled";
};

2
dts/arm/st/f4/stm32f437.dtsi
View file

@ -33,6 +33,7 @@
compatible = "st,stm32-uart";
reg = <0x40007800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
resets = <&rctl STM32_RESET(APB1, 30U)>;
interrupts = <82 0>;
status = "disabled";
};
@ -41,6 +42,7 @@
compatible = "st,stm32-uart";
reg = <0x40007c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
resets = <&rctl STM32_RESET(APB1, 31U)>;
interrupts = <83 0>;
status = "disabled";
};

3
dts/arm/st/f4/stm32f446.dtsi
View file

@ -26,6 +26,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
resets = <&rctl STM32_RESET(APB1, 18U)>;
interrupts = <39 0>;
status = "disabled";
};
@ -34,6 +35,7 @@
compatible ="st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
resets = <&rctl STM32_RESET(APB1, 19U)>;
interrupts = <52 0>;
status = "disabled";
};
@ -42,6 +44,7 @@
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
resets = <&rctl STM32_RESET(APB1, 20U)>;
interrupts = <53 0>;
status = "disabled";
};

8
dts/arm/st/f7/stm32f7.dtsi
View file

@ -224,6 +224,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000010>;
resets = <&rctl STM32_RESET(APB2, 4U)>;
interrupts = <37 0>;
status = "disabled";
};
@ -232,6 +233,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
resets = <&rctl STM32_RESET(APB1, 17U)>;
interrupts = <38 0>;
status = "disabled";
};
@ -240,6 +242,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
resets = <&rctl STM32_RESET(APB1, 18U)>;
interrupts = <39 0>;
status = "disabled";
};
@ -248,6 +251,7 @@
compatible ="st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
resets = <&rctl STM32_RESET(APB1, 19U)>;
interrupts = <52 0>;
status = "disabled";
};
@ -256,6 +260,7 @@
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
resets = <&rctl STM32_RESET(APB1, 20U)>;
interrupts = <53 0>;
status = "disabled";
};
@ -264,6 +269,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
resets = <&rctl STM32_RESET(APB2, 5U)>;
interrupts = <71 0>;
status = "disabled";
};
@ -272,6 +278,7 @@
compatible = "st,stm32-uart";
reg = <0x40007800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
resets = <&rctl STM32_RESET(APB1, 30U)>;
interrupts = <82 0>;
status = "disabled";
};
@ -280,6 +287,7 @@
compatible = "st,stm32-uart";
reg = <0x40007c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
resets = <&rctl STM32_RESET(APB1, 31U)>;
interrupts = <83 0>;
status = "disabled";
};

2
dts/arm/st/g0/stm32g0.dtsi
View file

@ -187,6 +187,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
resets = <&rctl STM32_RESET(APB1H, 14U)>;
interrupts = <27 0>;
status = "disabled";
};
@ -195,6 +196,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
resets = <&rctl STM32_RESET(APB1L, 17U)>;
interrupts = <28 0>;
status = "disabled";
};

1
dts/arm/st/g0/stm32g031.dtsi
View file

@ -13,6 +13,7 @@
compatible = "st,stm32-lpuart", "st,stm32-uart";
reg = <0x40008000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
resets = <&rctl STM32_RESET(APB1L, 20U)>;
interrupts = <29 0>;
status = "disabled";
};

2
dts/arm/st/g0/stm32g070.dtsi
View file

@ -13,6 +13,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
resets = <&rctl STM32_RESET(APB1L, 18U)>;
interrupts = <29 0>;
status = "disabled";
};
@ -21,6 +22,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
resets = <&rctl STM32_RESET(APB1L, 19U)>;
interrupts = <29 0>;
status = "disabled";
};

2
dts/arm/st/g0/stm32g071.dtsi
View file

@ -14,6 +14,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
resets = <&rctl STM32_RESET(APB1L, 18U)>;
interrupts = <29 0>;
status = "disabled";
};
@ -22,6 +23,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
resets = <&rctl STM32_RESET(APB1L, 19U)>;
interrupts = <29 0>;
status = "disabled";
};

2
dts/arm/st/g0/stm32g0b0.dtsi
View file

@ -22,6 +22,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
resets = <&rctl STM32_RESET(APB1L, 8U)>;
interrupts = <29 0>;
status = "disabled";
};
@ -30,6 +31,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000200>;
resets = <&rctl STM32_RESET(APB1L, 9U)>;
interrupts = <29 0>;
status = "disabled";
};

3
dts/arm/st/g0/stm32g0b1.dtsi
View file

@ -32,6 +32,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
resets = <&rctl STM32_RESET(APB1L, 8U)>;
interrupts = <29 0>;
status = "disabled";
};
@ -40,6 +41,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000200>;
resets = <&rctl STM32_RESET(APB1L, 9U)>;
interrupts = <29 0>;
status = "disabled";
};
@ -48,6 +50,7 @@
compatible = "st,stm32-lpuart", "st,stm32-uart";
reg = <0x40008400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
resets = <&rctl STM32_RESET(APB1L, 7U)>;
interrupts = <28 0>;
status = "disabled";
};

5
dts/arm/st/g4/stm32g4.dtsi
View file

@ -225,6 +225,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
resets = <&rctl STM32_RESET(APB2, 14U)>;
interrupts = <37 0>;
status = "disabled";
};
@ -233,6 +234,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
resets = <&rctl STM32_RESET(APB1L, 17U)>;
interrupts = <38 0>;
status = "disabled";
};
@ -241,6 +243,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
resets = <&rctl STM32_RESET(APB1L, 18U)>;
interrupts = <39 0>;
status = "disabled";
};
@ -249,6 +252,7 @@
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
resets = <&rctl STM32_RESET(APB1L, 19U)>;
interrupts = <52 0>;
status = "disabled";
};
@ -257,6 +261,7 @@
compatible = "st,stm32-lpuart", "st,stm32-uart";
reg = <0x40008000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000001>;
resets = <&rctl STM32_RESET(APB1H, 0U)>;
interrupts = <91 0>;
status = "disabled";
};

9
dts/arm/st/h7/stm32h7.dtsi
View file

@ -258,6 +258,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000010>;
resets = <&rctl STM32_RESET(APB2, 4U)>;
interrupts = <37 0>;
status = "disabled";
};
@ -265,6 +266,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
resets = <&rctl STM32_RESET(APB1L, 17U)>;
interrupts = <38 0>;
status = "disabled";
};
@ -272,6 +274,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
resets = <&rctl STM32_RESET(APB1L, 18U)>;
interrupts = <39 0>;
status = "disabled";
};
@ -279,6 +282,7 @@
compatible ="st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
resets = <&rctl STM32_RESET(APB1L, 19U)>;
interrupts = <52 0>;
status = "disabled";
};
@ -286,6 +290,7 @@
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
resets = <&rctl STM32_RESET(APB1L, 20U)>;
interrupts = <53 0>;
status = "disabled";
};
@ -293,6 +298,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
resets = <&rctl STM32_RESET(APB2, 5U)>;
interrupts = <71 0>;
status = "disabled";
};
@ -300,6 +306,7 @@
compatible = "st,stm32-uart";
reg = <0x40007800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
resets = <&rctl STM32_RESET(APB1L, 30U)>;
interrupts = <82 0>;
status = "disabled";
};
@ -307,6 +314,7 @@
compatible = "st,stm32-uart";
reg = <0x40007c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
resets = <&rctl STM32_RESET(APB1L, 31U)>;
interrupts = <83 0>;
status = "disabled";
};
@ -315,6 +323,7 @@
compatible = "st,stm32-lpuart", "st,stm32-uart";
reg = <0x58000c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00000008>;
resets = <&rctl STM32_RESET(APB4, 3U)>;
interrupts = <142 0>;
status = "disabled";
};

2
dts/arm/st/h7/stm32h723.dtsi
View file

@ -26,6 +26,7 @@
compatible = "st,stm32-uart";
reg = <0x40011800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000040>;
resets = <&rctl STM32_RESET(APB2, 6U)>;
interrupts = <155 0>;
status = "disabled";
};
@ -34,6 +35,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
resets = <&rctl STM32_RESET(APB2, 7U)>;
interrupts = <156 0>;
status = "disabled";
};

2
dts/arm/st/l0/stm32l0.dtsi
View file

@ -194,6 +194,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
resets = <&rctl STM32_RESET(APB1, 17U)>;
interrupts = <28 0>;
status = "disabled";
};
@ -202,6 +203,7 @@
compatible = "st,stm32-lpuart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
resets = <&rctl STM32_RESET(APB1, 18U)>;
interrupts = <29 0>;
status = "disabled";
};

1
dts/arm/st/l0/stm32l051.dtsi
View file

@ -34,6 +34,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
resets = <&rctl STM32_RESET(APB2, 14U)>;
interrupts = <27 0>;
status = "disabled";
};

3
dts/arm/st/l0/stm32l071.dtsi
View file

@ -112,6 +112,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
resets = <&rctl STM32_RESET(APB2, 14U)>;
interrupts = <27 0>;
status = "disabled";
};
@ -120,6 +121,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
resets = <&rctl STM32_RESET(APB1, 19U)>;
interrupts = <14 0>;
status = "disabled";
};
@ -128,6 +130,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
resets = <&rctl STM32_RESET(APB1, 20U)>;
interrupts = <14 0>;
status = "disabled";
};

5
dts/arm/st/l1/stm32l1.dtsi
View file

@ -122,6 +122,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
resets = <&rctl STM32_RESET(APB1, 17U)>;
interrupts = <38 0>;
status = "disabled";
};
@ -130,6 +131,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
resets = <&rctl STM32_RESET(APB1, 18U)>;
interrupts = <39 0>;
status = "disabled";
};
@ -138,6 +140,7 @@
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
resets = <&rctl STM32_RESET(APB1, 19U)>;
interrupts = <48 0>;
status = "disabled";
};
@ -146,6 +149,7 @@
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
resets = <&rctl STM32_RESET(APB1, 20U)>;
interrupts = <49 0>;
status = "disabled";
};
@ -198,6 +202,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
resets = <&rctl STM32_RESET(APB2, 14U)>;
interrupts = <37 0>;
status = "disabled";
};

3
dts/arm/st/l4/stm32l4.dtsi
View file

@ -175,6 +175,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
resets = <&rctl STM32_RESET(APB2, 14U)>;
interrupts = <37 0>;
status = "disabled";
};
@ -183,6 +184,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
resets = <&rctl STM32_RESET(APB1L, 17U)>;
interrupts = <38 0>;
status = "disabled";
};
@ -191,6 +193,7 @@
compatible = "st,stm32-lpuart", "st,stm32-uart";
reg = <0x40008000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000001>;
resets = <&rctl STM32_RESET(APB1H, 0U)>;
interrupts = <70 0>;
status = "disabled";
};

1
dts/arm/st/l4/stm32l431.dtsi
View file

@ -65,6 +65,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
resets = <&rctl STM32_RESET(APB1L, 18U)>;
interrupts = <39 0>;
status = "disabled";
};

1
dts/arm/st/l4/stm32l433.dtsi
View file

@ -52,6 +52,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
resets = <&rctl STM32_RESET(APB1L, 18U)>;
interrupts = <39 0>;
status = "disabled";
};

2
dts/arm/st/l4/stm32l452.dtsi
View file

@ -96,6 +96,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
resets = <&rctl STM32_RESET(APB1L, 18U)>;
interrupts = <39 0>;
status = "disabled";
};
@ -104,6 +105,7 @@
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
resets = <&rctl STM32_RESET(APB1L, 19U)>;
interrupts = <52 0>;
status = "disabled";
};

3
dts/arm/st/l4/stm32l471.dtsi
View file

@ -47,6 +47,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
resets = <&rctl STM32_RESET(APB1L, 18U)>;
interrupts = <39 0>;
status = "disabled";
};
@ -55,6 +56,7 @@
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
resets = <&rctl STM32_RESET(APB1L, 19U)>;
interrupts = <52 0>;
status = "disabled";
};
@ -63,6 +65,7 @@
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
resets = <&rctl STM32_RESET(APB1L, 20U)>;
interrupts = <53 0>;
status = "disabled";
};

3
dts/arm/st/l4/stm32l4r5.dtsi
View file

@ -73,6 +73,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
resets = <&rctl STM32_RESET(APB1L, 18U)>;
interrupts = <39 0>;
status = "disabled";
};
@ -81,6 +82,7 @@
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
resets = <&rctl STM32_RESET(APB1L, 19U)>;
interrupts = <52 0>;
status = "disabled";
};
@ -89,6 +91,7 @@
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
resets = <&rctl STM32_RESET(APB1L, 20U)>;
interrupts = <53 0>;
status = "disabled";
};

6
dts/arm/st/l5/stm32l5.dtsi
View file

@ -228,6 +228,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
resets = <&rctl STM32_RESET(APB2, 14U)>;
interrupts = <61 0>;
status = "disabled";
};
@ -236,6 +237,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
resets = <&rctl STM32_RESET(APB1L, 17U)>;
interrupts = <62 0>;
status = "disabled";
};
@ -244,6 +246,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
resets = <&rctl STM32_RESET(APB1L, 18U)>;
interrupts = <63 0>;
status = "disabled";
};
@ -252,6 +255,7 @@
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
resets = <&rctl STM32_RESET(APB1L, 19U)>;
interrupts = <64 0>;
status = "disabled";
};
@ -260,6 +264,7 @@
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
resets = <&rctl STM32_RESET(APB1L, 20U)>;
interrupts = <65 0>;
status = "disabled";
};
@ -268,6 +273,7 @@
compatible = "st,stm32-lpuart", "st,stm32-uart";
reg = <0x40008000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000001>;
resets = <&rctl STM32_RESET(APB1H, 0U)>;
interrupts = <66 0>;
status = "disabled";
};

7
dts/arm/st/mp1/stm32mp157.dtsi
View file

@ -248,6 +248,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x4000e000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
resets = <&rctl STM32_RESET(APB1, 14U)>;
interrupts = <38 0>;
status = "disabled";
};
@ -256,6 +257,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x4000f000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
resets = <&rctl STM32_RESET(APB1, 15U)>;
interrupts = <39 0>;
status = "disabled";
};
@ -264,6 +266,7 @@
compatible = "st,stm32-uart";
reg = <0x40010000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00010000>;
resets = <&rctl STM32_RESET(APB1, 16U)>;
interrupts = <52 0>;
status = "disabled";
};
@ -272,6 +275,7 @@
compatible = "st,stm32-uart";
reg = <0x40011000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
resets = <&rctl STM32_RESET(APB1, 17U)>;
interrupts = <53 0>;
status = "disabled";
};
@ -280,6 +284,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x44003000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
resets = <&rctl STM32_RESET(APB2, 13U)>;
interrupts = <71 0>;
status = "disabled";
};
@ -288,6 +293,7 @@
compatible = "st,stm32-uart";
reg = <0x40018000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
resets = <&rctl STM32_RESET(APB1, 18U)>;
interrupts = <82 0>;
status = "disabled";
};
@ -296,6 +302,7 @@
compatible = "st,stm32-uart";
reg = <0x40019000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
resets = <&rctl STM32_RESET(APB1, 19U)>;
interrupts = <83 0>;
status = "disabled";
};

6
dts/arm/st/u5/stm32u5.dtsi
View file

@ -248,6 +248,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
resets = <&rctl STM32_RESET(APB2, 14U)>;
interrupts = <61 0>;
status = "disabled";
};
@ -256,6 +257,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
resets = <&rctl STM32_RESET(APB1L, 17U)>;
interrupts = <62 0>;
status = "disabled";
};
@ -264,6 +266,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
resets = <&rctl STM32_RESET(APB1L, 18U)>;
interrupts = <63 0>;
status = "disabled";
};
@ -272,6 +275,7 @@
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
resets = <&rctl STM32_RESET(APB1L, 19U)>;
interrupts = <64 0>;
status = "disabled";
};
@ -280,6 +284,7 @@
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
resets = <&rctl STM32_RESET(APB1L, 20U)>;
interrupts = <65 0>;
status = "disabled";
};
@ -288,6 +293,7 @@
compatible = "st,stm32-lpuart", "st,stm32-uart";
reg = <0x46002400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000040>;
resets = <&rctl STM32_RESET(APB3, 6U)>;
interrupts = <66 0>;
status = "disabled";
};

2
dts/arm/st/wb/stm32wb.dtsi
View file

@ -218,6 +218,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
resets = <&rctl STM32_RESET(APB2, 14U)>;
interrupts = <36 0>;
status = "disabled";
};
@ -285,6 +286,7 @@
compatible = "st,stm32-lpuart", "st,stm32-uart";
reg = <0x40008000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000001>;
resets = <&rctl STM32_RESET(APB1H, 0U)>;
interrupts = <37 0>;
status = "disabled";
};

3
dts/arm/st/wl/stm32wl.dtsi
View file

@ -195,6 +195,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
resets = <&rctl STM32_RESET(APB2, 14U)>;
interrupts = <36 0>;
status = "disabled";
};
@ -203,6 +204,7 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
resets = <&rctl STM32_RESET(APB1L, 17U)>;
interrupts = <37 0>;
status = "disabled";
};
@ -211,6 +213,7 @@
compatible = "st,stm32-lpuart", "st,stm32-uart";
reg = <0x40008000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000001>;
resets = <&rctl STM32_RESET(APB1H, 0U)>;
interrupts = <38 0>;
status = "disabled";
};

5
dts/bindings/serial/st,stm32-uart-base.yaml
View file

@ -4,7 +4,7 @@
# Common fields for STM32 UART peripherals.
description: STM32 UART-BASE
include: [uart-controller.yaml, pinctrl-device.yaml]
include: [uart-controller.yaml, pinctrl-device.yaml, reset-device.yaml]
properties:
reg:
@ -13,6 +13,9 @@ properties:
clocks:
required: true
resets:
required: true
interrupts:
required: true