ioapic: cleanup code comments and doxygenize the file description
Use doxygen format for file documentation and move parameters to be part of the function comments. Change-Id: I01c0614e7cd3ef4c689d2aec3aa3e52e0d21ffcd Signed-off-by: Anas Nashif <anas.nashif@intel.com>
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Anas Nashif
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45a387fc46
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@ -1,5 +1,3 @@
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/* ioApicIntr.c - Intel IO APIC/xAPIC driver */
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/*
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* Copyright (c) 1997-1998, 2000-2002, 2004, 2006-2008, 2011-2015 Wind River
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*Systems, Inc.
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@ -31,48 +29,49 @@
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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DESCRIPTION
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This module is a driver for the IO APIC/xAPIC (Advanced Programmable
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Interrupt Controller) for P6 (PentiumPro, II, III) family processors
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and P7 (Pentium4) family processors. The IO APIC/xAPIC is included
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in the Intel's system chip set, such as ICH2. Software intervention
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may be required to enable the IO APIC/xAPIC in some chip sets.
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The 8259A interrupt controller is intended for use in a uni-processor
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system, IO APIC can be used in either a uni-processor or multi-processor
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system. The IO APIC handles interrupts very differently than the 8259A.
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Briefly, these differences are:
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- Method of Interrupt Transmission. The IO APIC transmits interrupts
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through a 3-wire bus and interrupts are handled without the need for
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the processor to run an interrupt acknowledge cycle.
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- Interrupt Priority. The priority of interrupts in the IO APIC is
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independent of the interrupt number. For example, interrupt 10 can
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be given a higher priority than interrupt 3.
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- More Interrupts. The IO APIC supports a total of 24 interrupts.
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The IO APIC unit consists of a set of interrupt input signals, a 24-entry
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by 64-bit Interrupt Redirection Table, programmable registers, and a message
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unit for sending and receiving APIC messages over the APIC bus or the
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Front-Side (system) bus. IO devices inject interrupts into the system by
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asserting one of the interrupt lines to the IO APIC. The IO APIC selects the
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corresponding entry in the Redirection Table and uses the information in that
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entry to format an interrupt request message. Each entry in the Redirection
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Table can be individually programmed to indicate edge/level sensitive interrupt
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signals, the interrupt vector and priority, the destination processor, and how
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the processor is selected (statically and dynamically). The information in
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the table is used to transmit a message to other APIC units (via the APIC bus
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or the Front-Side (system) bus). IO APIC is used in the Symmetric IO Mode.
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The base address of IO APIC is determined in loapic_init() and stored in the
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global variable ioApicBase and ioApicData.
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The lower 32 bit value of the redirection table entries for IRQ 0
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to 15 are edge triggered positive high, and for IRQ 16 to 23 are level
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triggered positive low.
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This implementation doesn't support multiple IO APICs.
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INCLUDE FILES: ioapic.h loapic.h
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SEE ALSO: loApicIntr.c
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/**
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* @file
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* @brief Intel IO APIC/xAPIC driver
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*
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* This module is a driver for the IO APIC/xAPIC (Advanced Programmable
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* Interrupt Controller) for P6 (PentiumPro, II, III) family processors
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* and P7 (Pentium4) family processors. The IO APIC/xAPIC is included
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* in the Intel's system chip set, such as ICH2. Software intervention
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* may be required to enable the IO APIC/xAPIC in some chip sets.
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* The 8259A interrupt controller is intended for use in a uni-processor
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* system, IO APIC can be used in either a uni-processor or multi-processor
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* system. The IO APIC handles interrupts very differently than the 8259A.
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* Briefly, these differences are:
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* - Method of Interrupt Transmission. The IO APIC transmits interrupts
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* through a 3-wire bus and interrupts are handled without the need for
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* the processor to run an interrupt acknowledge cycle.
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* - Interrupt Priority. The priority of interrupts in the IO APIC is
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* independent of the interrupt number. For example, interrupt 10 can
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* be given a higher priority than interrupt 3.
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* - More Interrupts. The IO APIC supports a total of 24 interrupts.
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*
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* The IO APIC unit consists of a set of interrupt input signals, a 24-entry
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* by 64-bit Interrupt Redirection Table, programmable registers, and a message
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* unit for sending and receiving APIC messages over the APIC bus or the
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* Front-Side (system) bus. IO devices inject interrupts into the system by
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* asserting one of the interrupt lines to the IO APIC. The IO APIC selects the
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* corresponding entry in the Redirection Table and uses the information in that
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* entry to format an interrupt request message. Each entry in the Redirection
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* Table can be individually programmed to indicate edge/level sensitive interrupt
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* signals, the interrupt vector and priority, the destination processor, and how
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* the processor is selected (statically and dynamically). The information in
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* the table is used to transmit a message to other APIC units (via the APIC bus
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* or the Front-Side (system) bus). IO APIC is used in the Symmetric IO Mode.
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* The base address of IO APIC is determined in loapic_init() and stored in the
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* global variable ioApicBase and ioApicData.
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* The lower 32 bit value of the redirection table entries for IRQ 0
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* to 15 are edge triggered positive high, and for IRQ 16 to 23 are level
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* triggered positive low.
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*
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* This implementation doesn't support multiple IO APICs.
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*
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* INCLUDE FILES: ioapic.h loapic.h
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*
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*/
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#include <nanokernel.h>
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@ -217,7 +216,6 @@ static void _IoApicRedUpdateLo(unsigned int irq, uint32_t value,
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*
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* @return N/A
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*/
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void _ioapic_init(void)
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{
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int32_t ix; /* redirection table index */
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@ -259,12 +257,11 @@ void _ioapic_init(void)
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* @brief Send EOI (End Of Interrupt) signal to IO APIC
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*
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* This routine sends an EOI signal to the IO APIC's interrupting source.
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* @param irq Interrupt number to send EOI
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*
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* @return N/A
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*/
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void _ioapic_eoi(unsigned int irq /* INT number to send EOI */
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)
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void _ioapic_eoi(unsigned int irq)
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{
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*(volatile unsigned int *)(CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_EOI) = irq;
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*(volatile unsigned int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_EOI) = 0;
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@ -276,16 +273,14 @@ void _ioapic_eoi(unsigned int irq /* INT number to send EOI */
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*
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* This routine returns EOI signalling information for a specific IRQ.
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*
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* @param irq IRQ number of interest
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* @param argRequired Pointer to "argument required" result area
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* @param arg Pointer to "argument value" result area
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* @return address of routine to be called to signal EOI;
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* as a side effect, also passes back indication if routine requires
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* an interrupt vector argument and what the argument value should be
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*/
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void *_ioapic_eoi_get(unsigned int irq, /* INTIN number of interest */
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char *argRequired, /* ptr to "argument required" result
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area */
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void **arg /* ptr to "argument value" result area */
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)
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void *_ioapic_eoi_get(unsigned int irq, char *argRequired, void **arg)
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{
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#ifndef XIOAPIC_DIRECT_ADDRESSING
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if (!(__IoApicGet(IOAPIC_VERS) & IOAPIC_PRQ)) {
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@ -316,12 +311,11 @@ void *_ioapic_eoi_get(unsigned int irq, /* INTIN number of interest */
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* @brief Enable a specified APIC interrupt input line
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*
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* This routine enables a specified APIC interrupt input line.
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* @param irq IRQ number to enable
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*
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* @return N/A
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*/
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void _ioapic_irq_enable(unsigned int irq /* INTIN number to enable */
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)
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void _ioapic_irq_enable(unsigned int irq)
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{
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_IoApicRedUpdateLo(irq, 0, IOAPIC_INT_MASK);
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}
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@ -331,12 +325,11 @@ void _ioapic_irq_enable(unsigned int irq /* INTIN number to enable */
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* @brief Disable a specified APIC interrupt input line
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*
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* This routine disables a specified APIC interrupt input line.
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* @param irq IRQ number to disable
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*
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* @return N/A
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*/
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void _ioapic_irq_disable(unsigned int irq /* INTIN number to disable */
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)
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void _ioapic_irq_disable(unsigned int irq)
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{
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_IoApicRedUpdateLo(irq, IOAPIC_INT_MASK, IOAPIC_INT_MASK);
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}
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@ -346,13 +339,13 @@ void _ioapic_irq_disable(unsigned int irq /* INTIN number to disable */
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* @brief Programs the interrupt redirection table
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*
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* This routine sets up the redirection table entry for the specified IRQ
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* @param irq Virtualized IRQ
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* @param vector Vector number
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* @param flags Interrupt flags
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*
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* @return N/A
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*/
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void _ioapic_irq_set(unsigned int irq, /* virtualized IRQ */
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unsigned int vector, /* vector number */
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uint32_t flags /* interrupt flags */
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)
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void _ioapic_irq_set(unsigned int irq, unsigned int vector, uint32_t flags)
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{
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uint32_t rteValue; /* value to copy into redirection table entry */
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@ -369,11 +362,11 @@ void _ioapic_irq_set(unsigned int irq, /* virtualized IRQ */
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* The routine writes the interrupt vector in the Interrupt Redirection
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* Table for specified irq number
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*
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* @param irq Interrupt number
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* @param vector Vector number
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* @return N/A
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*/
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void _ioapic_int_vec_set(unsigned int irq, /* INT number */
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unsigned int vector /* vector number */
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)
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void _ioapic_int_vec_set(unsigned int irq, unsigned int vector)
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{
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_IoApicRedUpdateLo(irq, vector, IOAPIC_VEC_MASK);
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}
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@ -385,13 +378,11 @@ void _ioapic_int_vec_set(unsigned int irq, /* INT number */
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* @brief Read a 32 bit IO APIC register
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*
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* This routine reads the specified IO APIC register using indirect addressing.
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* @param offset Register offset (8 bits)
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*
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* @return register value
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*/
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static uint32_t __IoApicGet(
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int32_t offset /* register offset (8 bits) */
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)
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static uint32_t __IoApicGet(int32_t offset)
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{
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uint32_t value; /* value */
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int key; /* interrupt lock level */
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@ -415,13 +406,11 @@ static uint32_t __IoApicGet(
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*
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* This routine writes the specified IO APIC register using indirect addressing.
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*
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* @param offset Register offset (8 bits)
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* @param value Value to set the register
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* @return N/A
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*/
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static void __IoApicSet(
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int32_t offset, /* register offset (8 bits) */
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uint32_t value /* value to set the register */
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)
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static void __IoApicSet(int32_t offset, uint32_t value)
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{
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int key; /* interrupt lock level */
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@ -443,11 +432,10 @@ static void __IoApicSet(
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*
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* This routine reads the low-order 32 bits of a Redirection Table entry.
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*
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* @param irq INTIN number
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* @return 32 low-order bits
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*/
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static uint32_t ioApicRedGetLo(unsigned int irq /* INTIN number */
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)
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static uint32_t ioApicRedGetLo(unsigned int irq)
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{
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#ifdef XIOAPIC_DIRECT_ADDRESSING
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volatile uint32_t *pEntry; /* pointer to redirection table entry */
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@ -469,12 +457,11 @@ static uint32_t ioApicRedGetLo(unsigned int irq /* INTIN number */
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*
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* This routine writes the low-order 32 bits of a Redirection Table entry.
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*
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* @param irq INTIN number
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* @param lower32 Value to be written
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* @return N/A
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*/
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static void ioApicRedSetLo(unsigned int irq, /* INTIN number */
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uint32_t lower32 /* value to be written */
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)
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static void ioApicRedSetLo(unsigned int irq, uint32_t lower32)
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{
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#ifdef XIOAPIC_DIRECT_ADDRESSING
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volatile uint32_t *pEntry; /* pointer to redirection table entry */
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@ -496,12 +483,11 @@ static void ioApicRedSetLo(unsigned int irq, /* INTIN number */
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*
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* This routine writes the high-order 32 bits of a Redirection Table entry.
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*
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* @param irq INTIN number
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* @param upper32 Value to be written
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* @return N/A
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*/
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static void ioApicRedSetHi(unsigned int irq, /* INTIN number */
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uint32_t upper32 /* value to be written */
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)
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static void ioApicRedSetHi(unsigned int irq, uint32_t upper32)
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{
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#ifdef XIOAPIC_DIRECT_ADDRESSING
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volatile uint32_t *pEntry; /* pointer to redirection table entry */
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@ -524,14 +510,14 @@ static void ioApicRedSetHi(unsigned int irq, /* INTIN number */
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* This routine modifies selected portions of the low-order 32 bits of a
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* Redirection Table entry, as indicated by the associate bit mask.
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*
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* @param irq INTIN number
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* @param value Value to be written
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* @param mask Mask of bits to be modified
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* @return N/A
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*/
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static void _IoApicRedUpdateLo(
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unsigned int irq, /* INTIN number */
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uint32_t value, /* value to be written */
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uint32_t mask /* mask of bits to be modified */
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)
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static void _IoApicRedUpdateLo(unsigned int irq,
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uint32_t value,
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uint32_t mask)
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{
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ioApicRedSetLo(irq, (ioApicRedGetLo(irq) & ~mask) | (value & mask));
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}
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@ -550,12 +536,11 @@ static void _IoApicRedUpdateLo(
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* This routine writes the specified 32-bit <value> into the RTE configuration
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* register for the specified <irq> (0 to (CONFIG_IOAPIC_NUM_RTES - 1))
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*
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* @return void
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* @param irq INTIN number
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* @param value Value to be written
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* @return N/A
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*/
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static void _IoApicRteConfigSet(unsigned int irq, /* INTIN number */
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uint32_t value /* value to be written */
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)
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static void _IoApicRteConfigSet(unsigned int irq, uint32_t value)
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{
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unsigned int offset; /* register offset */
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@ -577,10 +562,11 @@ static void _IoApicRteConfigSet(unsigned int irq, /* INTIN number */
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*
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* This routine writes the 32-bit <value> into the redirection register
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* specified by <reg>.
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* @param reg Register
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* @param value Value to be written
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*
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* @return void
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* @return N/A
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*/
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static void _IoApicRedirRegSet(unsigned int reg, uint32_t value)
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{
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unsigned int offset; /* register offset */
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