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arch/xtensa: adsp: add SRAM window 2 initialization

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Define SRAM window 2 details to the headers and open access to host to
the window in bootloader.

Also clarify Kconfig documentation that the semantics of the windows can
vary depending on which host<->DSP communication scheme is in use.

Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
This commit is contained in:
Kai Vehmanen 2022-06-29 16:44:57 +03:00 committed by Carles Cufí
parent be392fc23b
commit 45c82c9090
7 changed files with 33 additions and 3 deletions
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18
soc/xtensa/intel_adsp/Kconfig
View file

@ -47,13 +47,25 @@ config ADSP_WIN0_OFFSET
"firmware status register" at boot) within the reserved
region at the start of HP-SRAM.
config ADSP_WIN2_OFFSET
int "Byte offset of host window two"
default 32768
help
Offset of the second host shared memory window within
the reserved region at the start of HP-SRAM.
Typically used for debug output, but semantics can vary
depending on the host-firmware communication scheme that
is used.
config ADSP_WIN3_OFFSET
int "Byte offset of host window three"
default 40960
help
Offset of the fourth host shared memory window (used for
printk/log output) within the reserved region at the start
of HP-SRAM.
Offset of the second host shared memory window within
the reserved region at the start of HP-SRAM.
Typically used for debug output, but semantics can vary
depending on the host-firmware communication scheme that
is used.
config ADSP_TRACE_SIMCALL
bool "Emit SIMCALL output in addition to window tracing"

3
soc/xtensa/intel_adsp/ace_v1x/include/adsp_memory.h
View file

@ -25,6 +25,9 @@
/* Host shared memory windows */
#define HP_SRAM_WIN0_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN0_OFFSET)
#define HP_SRAM_WIN0_SIZE 0x2000
#define HP_SRAM_WIN2_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN2_OFFSET)
/* window 2 size is variable */
#define HP_SRAM_WIN2_SIZE (CONFIG_ADSP_WIN3_OFFSET - CONFIG_ADSP_WIN2_OFFSET)
#define HP_SRAM_WIN3_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN3_OFFSET)
#define HP_SRAM_WIN3_SIZE 0x2000

3
soc/xtensa/intel_adsp/cavs/include/intel_apl_adsp/adsp_memory.h
View file

@ -25,6 +25,9 @@
/* Host shared memory windows */
#define HP_SRAM_WIN0_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN0_OFFSET)
#define HP_SRAM_WIN0_SIZE 0x2000
#define HP_SRAM_WIN2_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN2_OFFSET)
/* window 2 size is variable */
#define HP_SRAM_WIN2_SIZE (CONFIG_ADSP_WIN3_OFFSET - CONFIG_ADSP_WIN2_OFFSET)
#define HP_SRAM_WIN3_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN3_OFFSET)
#define HP_SRAM_WIN3_SIZE 0x2000

3
soc/xtensa/intel_adsp/cavs/include/intel_cnl_adsp/adsp_memory.h
View file

@ -25,6 +25,9 @@
/* Host shared memory windows */
#define HP_SRAM_WIN0_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN0_OFFSET)
#define HP_SRAM_WIN0_SIZE 0x2000
#define HP_SRAM_WIN2_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN2_OFFSET)
/* window 2 size is variable */
#define HP_SRAM_WIN2_SIZE (CONFIG_ADSP_WIN3_OFFSET - CONFIG_ADSP_WIN2_OFFSET)
#define HP_SRAM_WIN3_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN3_OFFSET)
#define HP_SRAM_WIN3_SIZE 0x2000

3
soc/xtensa/intel_adsp/cavs/include/intel_icl_adsp/adsp_memory.h
View file

@ -25,6 +25,9 @@
/* Host shared memory windows */
#define HP_SRAM_WIN0_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN0_OFFSET)
#define HP_SRAM_WIN0_SIZE 0x2000
#define HP_SRAM_WIN2_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN2_OFFSET)
/* window 2 size is variable */
#define HP_SRAM_WIN2_SIZE (CONFIG_ADSP_WIN3_OFFSET - CONFIG_ADSP_WIN2_OFFSET)
#define HP_SRAM_WIN3_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN3_OFFSET)
#define HP_SRAM_WIN3_SIZE 0x2000

3
soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/adsp_memory.h
View file

@ -25,6 +25,9 @@
/* Host shared memory windows */
#define HP_SRAM_WIN0_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN0_OFFSET)
#define HP_SRAM_WIN0_SIZE 0x2000
#define HP_SRAM_WIN2_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN2_OFFSET)
/* window 2 size is variable */
#define HP_SRAM_WIN2_SIZE (CONFIG_ADSP_WIN3_OFFSET - CONFIG_ADSP_WIN2_OFFSET)
#define HP_SRAM_WIN3_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN3_OFFSET)
#define HP_SRAM_WIN3_SIZE 0x2000

3
soc/xtensa/intel_adsp/common/boot.c
View file

@ -145,6 +145,9 @@ __imr void win_setup(void)
CAVS_WIN[0].dmwba = (HP_SRAM_WIN0_BASE | CAVS_DMWBA_READONLY
| CAVS_DMWBA_ENABLE);
CAVS_WIN[2].dmwlo = HP_SRAM_WIN2_SIZE | 0x7;
CAVS_WIN[2].dmwba = (HP_SRAM_WIN2_BASE | CAVS_DMWBA_ENABLE);
CAVS_WIN[3].dmwlo = HP_SRAM_WIN3_SIZE | 0x7;
CAVS_WIN[3].dmwba = (HP_SRAM_WIN3_BASE | CAVS_DMWBA_READONLY
| CAVS_DMWBA_ENABLE);