dma: stm32f4x: Use terminology found in the datasheet
Each controller contains a number of streams. Subsequently each stream contains a number of channels. Channels are selectable via the stream's control register. Change-Id: Ib75d1377cb8fc38f27e4566b275343b2ffb8da65 Signed-off-by: Lee Jones <lee.jones@linaro.org>
This commit is contained in:
Lee Jones
parent
ec60772103
commit
45fc0ac496
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@ -18,21 +18,21 @@
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#include <clock_control/stm32_clock_control.h>
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#define DMA_STM32_MAX_CHANNELS 8 /* Number of channels per controller */
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#define DMA_STM32_MAX_STREAMS 8 /* Number of streams per controller */
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#define DMA_STM32_MAX_DEVS 2 /* Number of controllers */
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#define DMA_STM32_1 0 /* First DMA controller */
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#define DMA_STM32_2 1 /* Second DMA controller */
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#define DMA_STM32_IRQ_PRI CONFIG_DMA_0_IRQ_PRI
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struct dma_stm32_chan_reg {
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struct dma_stm32_stream_reg {
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/* Shared registers */
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uint32_t lisr;
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uint32_t hisr;
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uint32_t lifcr;
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uint32_t hifcr;
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/* Per channel registers */
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/* Per stream registers */
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uint32_t scr;
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uint32_t sndtr;
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uint32_t spar;
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@ -41,21 +41,21 @@ struct dma_stm32_chan_reg {
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uint32_t sfcr;
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};
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struct dma_stm32_chan {
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struct dma_stm32_stream {
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uint32_t id;
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uint32_t direction;
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struct device *dev;
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struct dma_stm32_chan_reg regs;
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struct dma_stm32_stream_reg regs;
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bool busy;
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void (*dma_callback)(struct device *dev, uint32_t channel,
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void (*dma_callback)(struct device *dev, uint32_t id,
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int error_code);
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};
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static struct dma_stm32_device {
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uint32_t base;
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struct device *clk;
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struct dma_stm32_chan chan[DMA_STM32_MAX_CHANNELS];
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struct dma_stm32_stream stream[DMA_STM32_MAX_STREAMS];
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bool mem2mem;
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} ddata[DMA_STM32_MAX_DEVS];
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@ -180,16 +180,16 @@ static void dma_stm32_write(struct dma_stm32_device *ddata,
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sys_write32(val, ddata->base + reg);
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}
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static void dma_stm32_dump_reg(struct dma_stm32_device *ddata, uint32_t channel)
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static void dma_stm32_dump_reg(struct dma_stm32_device *ddata, uint32_t id)
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{
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uint32_t scr = dma_stm32_read(ddata, DMA_STM32_SCR(channel));
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uint32_t ndtr = dma_stm32_read(ddata, DMA_STM32_SNDTR(channel));
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uint32_t spar = dma_stm32_read(ddata, DMA_STM32_SPAR(channel));
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uint32_t sm0ar = dma_stm32_read(ddata, DMA_STM32_SM0AR(channel));
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uint32_t sm1ar = dma_stm32_read(ddata, DMA_STM32_SM1AR(channel));
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uint32_t sfcr = dma_stm32_read(ddata, DMA_STM32_SFCR(channel));
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uint32_t scr = dma_stm32_read(ddata, DMA_STM32_SCR(id));
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uint32_t ndtr = dma_stm32_read(ddata, DMA_STM32_SNDTR(id));
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uint32_t spar = dma_stm32_read(ddata, DMA_STM32_SPAR(id));
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uint32_t sm0ar = dma_stm32_read(ddata, DMA_STM32_SM0AR(id));
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uint32_t sm1ar = dma_stm32_read(ddata, DMA_STM32_SM1AR(id));
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uint32_t sfcr = dma_stm32_read(ddata, DMA_STM32_SFCR(id));
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SYS_LOG_INF("Using channel: %d\n", channel);
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SYS_LOG_INF("Using stream: %d\n", id);
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SYS_LOG_INF("SCR: 0x%x \t(config)\n", scr);
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SYS_LOG_INF("NDTR: 0x%x \t(length)\n", ndtr);
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SYS_LOG_INF("SPAR: 0x%x \t(source)\n", spar);
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@ -199,84 +199,84 @@ static void dma_stm32_dump_reg(struct dma_stm32_device *ddata, uint32_t channel)
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}
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static uint32_t dma_stm32_irq_status(struct dma_stm32_device *ddata,
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uint32_t channel)
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uint32_t id)
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{
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uint32_t irqs;
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if (channel & 4) {
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if (id & 4) {
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irqs = dma_stm32_read(ddata, DMA_STM32_HISR);
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} else {
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irqs = dma_stm32_read(ddata, DMA_STM32_LISR);
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}
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return (irqs >> (((channel & 2) << 3) | ((channel & 1) * 6)));
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return (irqs >> (((id & 2) << 3) | ((id & 1) * 6)));
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}
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static void dma_stm32_irq_clear(struct dma_stm32_device *ddata,
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uint32_t channel, uint32_t irqs)
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uint32_t id, uint32_t irqs)
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{
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irqs = irqs << (((channel & 2) << 3) | ((channel & 1) * 6));
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irqs = irqs << (((id & 2) << 3) | ((id & 1) * 6));
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if (channel & 4) {
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if (id & 4) {
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dma_stm32_write(ddata, DMA_STM32_HIFCR, irqs);
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} else {
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dma_stm32_write(ddata, DMA_STM32_LIFCR, irqs);
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}
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}
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static void dma_stm32_irq_handler(void *arg, uint32_t channel)
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static void dma_stm32_irq_handler(void *arg, uint32_t id)
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{
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struct device *dev = arg;
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struct dma_stm32_device *ddata = dev->driver_data;
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struct dma_stm32_chan *chan = &ddata->chan[channel];
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struct dma_stm32_stream *stream = &ddata->stream[id];
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uint32_t irqstatus, config, sfcr;
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irqstatus = dma_stm32_irq_status(ddata, channel);
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config = dma_stm32_read(ddata, DMA_STM32_SCR(channel));
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sfcr = dma_stm32_read(ddata, DMA_STM32_SFCR(channel));
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irqstatus = dma_stm32_irq_status(ddata, id);
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config = dma_stm32_read(ddata, DMA_STM32_SCR(id));
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sfcr = dma_stm32_read(ddata, DMA_STM32_SFCR(id));
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/* Silently ignore spurious transfer half complete IRQ */
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if (irqstatus & DMA_STM32_HTI) {
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dma_stm32_irq_clear(ddata, channel, DMA_STM32_HTI);
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dma_stm32_irq_clear(ddata, id, DMA_STM32_HTI);
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return;
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}
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chan->busy = false;
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stream->busy = false;
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if ((irqstatus & DMA_STM32_TCI) && (config & DMA_STM32_SCR_TCIE)) {
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dma_stm32_irq_clear(ddata, channel, DMA_STM32_TCI);
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dma_stm32_irq_clear(ddata, id, DMA_STM32_TCI);
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chan->dma_callback(chan->dev, channel, 0);
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stream->dma_callback(stream->dev, id, 0);
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} else {
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SYS_LOG_ERR("Internal error: IRQ status: 0x%x\n", irqstatus);
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dma_stm32_irq_clear(ddata, channel, irqstatus);
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dma_stm32_irq_clear(ddata, id, irqstatus);
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chan->dma_callback(chan->dev, channel, -EIO);
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stream->dma_callback(stream->dev, id, -EIO);
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}
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}
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static int dma_stm32_disable_chan(struct dma_stm32_device *ddata,
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uint32_t channel)
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static int dma_stm32_disable_stream(struct dma_stm32_device *ddata,
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uint32_t id)
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{
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uint32_t config;
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int count = 0;
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int ret = 0;
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for (;;) {
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config = dma_stm32_read(ddata, DMA_STM32_SCR(channel));
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/* Channel already disabled */
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config = dma_stm32_read(ddata, DMA_STM32_SCR(id));
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/* Stream already disabled */
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if (!(config & DMA_STM32_SCR_EN)) {
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return 0;
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}
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/* Try to disable channel */
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dma_stm32_write(ddata, DMA_STM32_SCR(channel),
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/* Try to disable stream */
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dma_stm32_write(ddata, DMA_STM32_SCR(id),
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config &= ~DMA_STM32_SCR_EN);
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/* After trying for 5 seconds, give up */
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k_sleep(K_SECONDS(5));
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if (count++ > (5 * 1000) / 50) {
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SYS_LOG_ERR("DMA error: Channel in use\n");
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SYS_LOG_ERR("DMA error: Stream in use\n");
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return -EBUSY;
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}
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}
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@ -284,12 +284,12 @@ static int dma_stm32_disable_chan(struct dma_stm32_device *ddata,
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return ret;
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}
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static int dma_stm32_config_devcpy(struct device *dev, uint32_t channel,
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static int dma_stm32_config_devcpy(struct device *dev, uint32_t id,
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struct dma_config *config)
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{
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struct dma_stm32_device *ddata = dev->driver_data;
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struct dma_stm32_chan_reg *regs = &ddata->chan[channel].regs;
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struct dma_stm32_stream_reg *regs = &ddata->stream[id].regs;
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uint32_t src_bus_width = dma_width_index(config->source_data_size);
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uint32_t dst_bus_width = dma_width_index(config->dest_data_size);
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uint32_t src_burst_size = dma_burst_index(config->source_burst_length);
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@ -331,10 +331,10 @@ static int dma_stm32_config_devcpy(struct device *dev, uint32_t channel,
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return 0;
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}
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static int dma_stm32_config_memcpy(struct device *dev, uint32_t channel)
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static int dma_stm32_config_memcpy(struct device *dev, uint32_t id)
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{
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struct dma_stm32_device *ddata = dev->driver_data;
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struct dma_stm32_chan_reg *regs = &ddata->chan[channel].regs;
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struct dma_stm32_stream_reg *regs = &ddata->stream[id].regs;
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regs->scr = DMA_STM32_SCR_DIR(DMA_STM32_MEM_TO_MEM) |
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DMA_STM32_SCR_MINC | /* Memory increment mode */
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@ -349,15 +349,15 @@ static int dma_stm32_config_memcpy(struct device *dev, uint32_t channel)
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return 0;
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}
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static int dma_stm32_config(struct device *dev, uint32_t channel,
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static int dma_stm32_config(struct device *dev, uint32_t id,
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struct dma_config *config)
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{
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struct dma_stm32_device *ddata = dev->driver_data;
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struct dma_stm32_chan *chan = &ddata->chan[channel];
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struct dma_stm32_chan_reg *regs = &ddata->chan[channel].regs;
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struct dma_stm32_stream *stream = &ddata->stream[id];
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struct dma_stm32_stream_reg *regs = &ddata->stream[id].regs;
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int ret;
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if (chan->busy) {
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if (stream->busy) {
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return -EBUSY;
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}
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@ -367,11 +367,11 @@ static int dma_stm32_config(struct device *dev, uint32_t channel,
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return -EINVAL;
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}
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chan->busy = true;
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chan->dma_callback = config->dma_callback;
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chan->direction = config->channel_direction;
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stream->busy = true;
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stream->dma_callback = config->dma_callback;
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stream->direction = config->channel_direction;
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if (chan->direction == MEMORY_TO_PERIPHERAL) {
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if (stream->direction == MEMORY_TO_PERIPHERAL) {
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regs->sm0ar = (uint32_t)config->head_block->source_address;
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regs->spar = (uint32_t)config->head_block->dest_address;
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} else {
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@ -379,10 +379,10 @@ static int dma_stm32_config(struct device *dev, uint32_t channel,
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regs->sm0ar = (uint32_t)config->head_block->dest_address;
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}
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if (chan->direction == MEMORY_TO_MEMORY) {
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ret = dma_stm32_config_memcpy(dev, stream);
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if (stream->direction == MEMORY_TO_MEMORY) {
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ret = dma_stm32_config_memcpy(dev, id);
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} else {
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ret = dma_stm32_config_devcpy(dev, stream, config);
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ret = dma_stm32_config_devcpy(dev, id, config);
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}
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regs->sndtr = config->head_block->block_size;
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@ -390,69 +390,69 @@ static int dma_stm32_config(struct device *dev, uint32_t channel,
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return ret;
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}
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static int dma_stm32_start(struct device *dev, uint32_t channel)
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static int dma_stm32_start(struct device *dev, uint32_t id)
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{
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struct dma_stm32_device *ddata = dev->driver_data;
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struct dma_stm32_chan_reg *regs = &ddata->chan[channel].regs;
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struct dma_stm32_stream_reg *regs = &ddata->stream[id].regs;
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uint32_t irqstatus;
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int ret;
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ret = dma_stm32_disable_chan(ddata, channel);
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ret = dma_stm32_disable_stream(ddata, id);
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if (ret) {
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return ret;
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}
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dma_stm32_write(ddata, DMA_STM32_SCR(channel), regs->scr);
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dma_stm32_write(ddata, DMA_STM32_SPAR(channel), regs->spar);
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dma_stm32_write(ddata, DMA_STM32_SM0AR(channel), regs->sm0ar);
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dma_stm32_write(ddata, DMA_STM32_SFCR(channel), regs->sfcr);
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dma_stm32_write(ddata, DMA_STM32_SM1AR(channel), regs->sm1ar);
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dma_stm32_write(ddata, DMA_STM32_SNDTR(channel), regs->sndtr);
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dma_stm32_write(ddata, DMA_STM32_SCR(id), regs->scr);
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dma_stm32_write(ddata, DMA_STM32_SPAR(id), regs->spar);
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dma_stm32_write(ddata, DMA_STM32_SM0AR(id), regs->sm0ar);
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dma_stm32_write(ddata, DMA_STM32_SFCR(id), regs->sfcr);
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dma_stm32_write(ddata, DMA_STM32_SM1AR(id), regs->sm1ar);
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dma_stm32_write(ddata, DMA_STM32_SNDTR(id), regs->sndtr);
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/* Clear remanent IRQs from previous transfers */
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irqstatus = dma_stm32_irq_status(ddata, channel);
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irqstatus = dma_stm32_irq_status(ddata, id);
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if (irqstatus) {
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dma_stm32_irq_clear(ddata, channel, irqstatus);
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dma_stm32_irq_clear(ddata, id, irqstatus);
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}
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dma_stm32_dump_reg(ddata, channel);
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dma_stm32_dump_reg(ddata, id);
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/* Push the start button */
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dma_stm32_write(ddata, DMA_STM32_SCR(channel),
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dma_stm32_write(ddata, DMA_STM32_SCR(id),
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regs->scr | DMA_STM32_SCR_EN);
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return 0;
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}
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static int dma_stm32_stop(struct device *dev, uint32_t channel)
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static int dma_stm32_stop(struct device *dev, uint32_t id)
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{
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struct dma_stm32_device *ddata = dev->driver_data;
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struct dma_stm32_chan *chan = &ddata->chan[stream];
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struct dma_stm32_stream *stream = &ddata->stream[id];
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uint32_t scr, sfcr, irqstatus;
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int ret;
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/* Disable all IRQs */
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scr = dma_stm32_read(ddata, DMA_STM32_SCR(channel));
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scr = dma_stm32_read(ddata, DMA_STM32_SCR(id));
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scr &= ~DMA_STM32_SCR_IRQ_MASK;
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dma_stm32_write(ddata, DMA_STM32_SCR(channel), scr);
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dma_stm32_write(ddata, DMA_STM32_SCR(id), scr);
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sfcr = dma_stm32_read(ddata, DMA_STM32_SFCR(channel));
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sfcr = dma_stm32_read(ddata, DMA_STM32_SFCR(id));
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sfcr &= ~DMA_STM32_SFCR_FEIE;
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dma_stm32_write(ddata, DMA_STM32_SFCR(channel), sfcr);
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dma_stm32_write(ddata, DMA_STM32_SFCR(id), sfcr);
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/* Disable channel */
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ret = dma_stm32_disable_chan(ddata, channel);
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/* Disable stream */
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ret = dma_stm32_disable_stream(ddata, id);
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if (ret)
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return ret;
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/* Clear remanent IRQs from previous transfers */
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irqstatus = dma_stm32_irq_status(ddata, stream);
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irqstatus = dma_stm32_irq_status(ddata, id);
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if (irqstatus) {
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dma_stm32_irq_clear(ddata, channel, irqstatus);
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dma_stm32_irq_clear(ddata, id, irqstatus);
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}
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/* Finally, flag channel as free */
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chan->busy = false;
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/* Finally, flag stream as free */
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stream->busy = false;
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return 0;
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}
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@ -463,10 +463,10 @@ static int dma_stm32_init(struct device *dev)
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const struct dma_stm32_config *cdata = dev->config->config_info;
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int i;
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for (i = 0; i < DMA_STM32_MAX_CHANNELS; i++) {
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ddata->chan[i].id = i;
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ddata->chan[i].dev = dev;
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ddata->chan[i].busy = false;
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for (i = 0; i < DMA_STM32_MAX_STREAMS; i++) {
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ddata->stream[i].id = i;
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ddata->stream[i].dev = dev;
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ddata->stream[i].busy = false;
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}
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/* Enable DMA clock */
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