ext: mcux: Remove clock_config.c/h
We have never used the mcux clock_config.c/h files, so remove them. We configure clocks in soc.c instead to allow more options with Kconfigs. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This commit is contained in:
Maureen Helm
Kumar Gala
parent
adf5b36a78
commit
4624f13290
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@ -1,184 +0,0 @@
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/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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||||
*
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||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
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*
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||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
|
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* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
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||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* How to set up clock using clock driver functions:
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*
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* 1. Setup clock sources.
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*
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* 2. Setup voltage for the fastest of the clock outputs
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*
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* 3. Set up wait states of the flash.
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*
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* 4. Set up all dividers.
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*
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* 5. Set up all selectors to provide selected clocks.
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*/
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/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
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!!ClocksProfile
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product: Clocks v1.0
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processor: LPC54114J256
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package_id: LPC54114J256BD64
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mcu_data: ksdk2_0
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processor_version: 1.1.0
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board: LPCXpresso54114
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
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#include "fsl_power.h"
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#include "fsl_clock.h"
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#include "clock_config.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/* System clock frequency. */
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extern uint32_t SystemCoreClock;
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/*******************************************************************************
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********************* Configuration BOARD_BootClockFRO12M ***********************
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******************************************************************************/
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/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
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!!Configuration
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name: BOARD_BootClockFRO12M
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outputs:
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- {id: System_clock.outFreq, value: 12 MHz}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
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/*******************************************************************************
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* Variables for BOARD_BootClockFRO12M configuration
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******************************************************************************/
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/*******************************************************************************
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* Code for BOARD_BootClockFRO12M configuration
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******************************************************************************/
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void BOARD_BootClockFRO12M(void)
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{
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/*!< Set up the clock sources */
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/*!< Set up FRO */
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POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
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CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
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being below the voltage for current speed */
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CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
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POWER_SetVoltageForFreq(12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
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CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
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/*!< Set up dividers */
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
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/*!< Set SystemCoreClock variable. */
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SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
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}
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/*******************************************************************************
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********************** Configuration BOARD_BootClockFROHF48M ***********************
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******************************************************************************/
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/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
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!!Configuration
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name: BOARD_BootClockFROHF48M
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outputs:
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- {id: System_clock.outFreq, value: 48 MHz}
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settings:
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- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
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/*******************************************************************************
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* Variables for BOARD_BootClockFROHF48M configuration
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******************************************************************************/
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/*******************************************************************************
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* Code for BOARD_BootClockFROHF48M configuration
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******************************************************************************/
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void BOARD_BootClockFROHF48M(void)
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{
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/*!< Set up the clock sources */
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/*!< Set up FRO */
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POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
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CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
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being below the voltage for current speed */
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POWER_SetVoltageForFreq(48000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
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CLOCK_SetFLASHAccessCyclesForFreq(48000000U); /*!< Set FLASH wait states for core */
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CLOCK_SetupFROClocking(48000000U); /*!< Set up high frequency FRO output to selected frequency */
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/*!< Set up dividers */
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
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/*!< Set SystemCoreClock variable. */
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SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
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}
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/*******************************************************************************
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********************* Configuration BOARD_BootClockFROHF96M **********************
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******************************************************************************/
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/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
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!!Configuration
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name: BOARD_BootClockFROHF96M
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outputs:
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- {id: System_clock.outFreq, value: 96 MHz}
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settings:
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- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
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sources:
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- {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
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/*******************************************************************************
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* Variables for BOARD_BootClockFROHF96M configuration
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******************************************************************************/
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/*******************************************************************************
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* Code for BOARD_BootClockFROHF96M configuration
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******************************************************************************/
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void BOARD_BootClockFROHF96M(void)
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{
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/*!< Set up the clock sources */
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/*!< Set up FRO */
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POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
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CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
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being below the voltage for current speed */
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POWER_SetVoltageForFreq(96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
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CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
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CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */
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/*!< Set up dividers */
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
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/*!< Set SystemCoreClock variable. */
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SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
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}
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@ -1,120 +0,0 @@
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/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
|
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
|
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _CLOCK_CONFIG_H_
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#define _CLOCK_CONFIG_H_
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#include "fsl_common.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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#define BOARD_XTAL0_CLK_HZ 12000000U /*!< Board xtal0 frequency in Hz */
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#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */
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#define BOARD_BootClockRUN BOARD_BootClockFROHF48M
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/*******************************************************************************
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********************* Configuration BOARD_BootClockFRO12M ***********************
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******************************************************************************/
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/*******************************************************************************
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* Definitions for BOARD_BootClockFRO12M configuration
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******************************************************************************/
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#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */
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/*******************************************************************************
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* API for BOARD_BootClockFRO12M configuration
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif /* __cplusplus*/
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/*!
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* @brief This function executes configuration of clocks.
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*
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*/
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void BOARD_BootClockFRO12M(void);
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#if defined(__cplusplus)
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}
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#endif /* __cplusplus*/
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/*******************************************************************************
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********************** Configuration BOARD_BootClockFROHF48M ***********************
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******************************************************************************/
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/*******************************************************************************
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* Definitions for BOARD_BootClockFROHF48M configuration
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******************************************************************************/
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#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
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/*******************************************************************************
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* API for BOARD_BootClockFROHF48M configuration
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif /* __cplusplus*/
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/*!
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* @brief This function executes configuration of clocks.
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*
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*/
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void BOARD_BootClockFROHF48M(void);
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#if defined(__cplusplus)
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}
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#endif /* __cplusplus*/
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/*******************************************************************************
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********************* Configuration BOARD_BootClockFROHF96M **********************
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******************************************************************************/
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/*******************************************************************************
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* Definitions for BOARD_BootClockFROHF96M configuration
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******************************************************************************/
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#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */
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/*******************************************************************************
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* API for BOARD_BootClockFROHF96M configuration
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif /* __cplusplus*/
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/*!
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* @brief This function executes configuration of clocks.
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*
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*/
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void BOARD_BootClockFROHF96M(void);
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#if defined(__cplusplus)
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}
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#endif /* __cplusplus*/
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#endif /* _CLOCK_CONFIG_H_ */
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@ -1,107 +0,0 @@
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/*
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* Copyright 2017 NXP
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*
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* Redistribution and use in source and binary forms, with or without modification,
|
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* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
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#include "fsl_common.h"
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#include "clock_config.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/* ARM PLL configuration for RUN mode */
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const clock_arm_pll_config_t armPllConfig = {.loopDivider = 100U};
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/* SYS PLL configuration for RUN mode */
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const clock_sys_pll_config_t sysPllConfig = {.loopDivider = 1U};
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/* USB1 PLL configuration for RUN mode */
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const clock_usb_pll_config_t usb1PllConfig = {.loopDivider = 0U};
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/* System clock frequency. */
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extern uint32_t SystemCoreClock;
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/*******************************************************************************
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* Code
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******************************************************************************/
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static void BOARD_BootClockGate(void)
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{
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/* Disable all unused peripheral clock */
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CCM->CCGR0 = 0x00C0000FU;
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CCM->CCGR1 = 0x30000000U;
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CCM->CCGR2 = 0xFF3F303FU;
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CCM->CCGR3 = 0xF0000330U;
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CCM->CCGR4 = 0x0000FF3CU;
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CCM->CCGR5 = 0xF003330FU;
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CCM->CCGR6 = 0x00FC0F00U;
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}
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void BOARD_BootClockRUN(void)
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{
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/* Boot ROM did initialize the XTAL, here we only sets external XTAL OSC freq */
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CLOCK_SetXtalFreq(24000000U);
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CLOCK_SetRtcXtalFreq(32768U);
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CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0x1); /* Set PERIPH_CLK2 MUX to OSC */
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CLOCK_SetMux(kCLOCK_PeriphMux, 0x1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
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/* Setting the VDD_SOC to 1.5V. It is necessary to config AHB to 600Mhz */
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DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
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CLOCK_InitArmPll(&armPllConfig); /* Configure ARM PLL to 1200M */
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#ifndef SKIP_SYSCLK_INIT
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CLOCK_InitSysPll(&sysPllConfig); /* Configure SYS PLL to 528M */
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#endif
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#ifndef SKIP_USB_PLL_INIT
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CLOCK_InitUsb1Pll(&usb1PllConfig); /* Configure USB1 PLL to 480M */
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#endif
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CLOCK_SetDiv(kCLOCK_ArmDiv, 0x1); /* Set ARM PODF to 0, divide by 2 */
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CLOCK_SetDiv(kCLOCK_AhbDiv, 0x0); /* Set AHB PODF to 0, divide by 1 */
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CLOCK_SetDiv(kCLOCK_IpgDiv, 0x3); /* Set IPG PODF to 3, divede by 4 */
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CLOCK_SetMux(kCLOCK_PrePeriphMux, 0x3); /* Set PRE_PERIPH_CLK to PLL1, 1200M */
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CLOCK_SetMux(kCLOCK_PeriphMux, 0x0); /* Set PERIPH_CLK MUX to PRE_PERIPH_CLK */
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/* Disable unused clock */
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BOARD_BootClockGate();
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/* Power down all unused PLL */
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CLOCK_DeinitAudioPll();
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CLOCK_DeinitVideoPll();
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CLOCK_DeinitEnetPll();
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CLOCK_DeinitUsb2Pll();
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/* Configure UART divider to default */
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CLOCK_SetMux(kCLOCK_UartMux, 0); /* Set UART source to PLL3 80M */
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CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set UART divider to 1 */
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/* Update core clock */
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SystemCoreClockUpdate();
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}
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@ -1,50 +0,0 @@
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/*
|
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* Copyright 2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _CLOCK_CONFIG_H_
|
||||
#define _CLOCK_CONFIG_H_
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#define BOARD_XTAL0_CLK_HZ 24000000U
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
void BOARD_BootClockRUN(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
#endif /* _CLOCK_CONFIG_H_ */
|
||||
|
|
@ -1,311 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* How to setup clock using clock driver functions:
|
||||
*
|
||||
* 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
|
||||
* and flash clock are in allowed range during clock mode switch.
|
||||
*
|
||||
* 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
|
||||
*
|
||||
* 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
|
||||
* internal reference clock(MCGIRCLK). Follow the steps to setup:
|
||||
*
|
||||
* 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
|
||||
*
|
||||
* 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
|
||||
* correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
|
||||
* explicitly to setup MCGIRCLK.
|
||||
*
|
||||
* 3). Don't need to configure FLL explicitly, because if target mode is FLL
|
||||
* mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
|
||||
* if the target mode is not FLL mode, the FLL is disabled.
|
||||
*
|
||||
* 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
|
||||
* setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
|
||||
* be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
|
||||
*
|
||||
* 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
|
||||
*/
|
||||
|
||||
/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
|
||||
!!ClocksProfile
|
||||
product: Clocks v1.0
|
||||
processor: MK64FN1M0xxx12
|
||||
package_id: MK64FN1M0VLL12
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 1.0.1
|
||||
board: FRDM-K64F
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
|
||||
|
||||
#include "fsl_smc.h"
|
||||
#include "clock_config.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */
|
||||
#define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */
|
||||
#define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */
|
||||
#define SIM_OSC32KSEL_RTC32KCLK_CLK 2U /*!< OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
|
||||
#define SIM_PLLFLLSEL_IRC48MCLK_CLK 3U /*!< PLLFLL select: IRC48MCLK clock */
|
||||
#define SIM_PLLFLLSEL_MCGPLLCLK_CLK 1U /*!< PLLFLL select: MCGPLLCLK clock */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/* System clock frequency. */
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : CLOCK_CONFIG_SetFllExtRefDiv
|
||||
* Description : Configure FLL external reference divider (FRDIV).
|
||||
* Param frdiv : The value to set FRDIV.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)
|
||||
{
|
||||
MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
********************** Configuration BOARD_BootClockRUN ***********************
|
||||
******************************************************************************/
|
||||
/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockRUN
|
||||
outputs:
|
||||
- {id: Bus_clock.outFreq, value: 60 MHz}
|
||||
- {id: Core_clock.outFreq, value: 120 MHz, locked: true, accuracy: '0.001'}
|
||||
- {id: Flash_clock.outFreq, value: 24 MHz}
|
||||
- {id: FlexBus_clock.outFreq, value: 40 MHz}
|
||||
- {id: LPO_clock.outFreq, value: 1 kHz}
|
||||
- {id: MCGFFCLK.outFreq, value: 1.5625 MHz}
|
||||
- {id: MCGIRCLK.outFreq, value: 32.768 kHz}
|
||||
- {id: OSCERCLK.outFreq, value: 50 MHz}
|
||||
- {id: PLLFLLCLK.outFreq, value: 120 MHz}
|
||||
- {id: System_clock.outFreq, value: 120 MHz}
|
||||
settings:
|
||||
- {id: MCGMode, value: PEE}
|
||||
- {id: MCG.FCRDIV.scale, value: '1', locked: true}
|
||||
- {id: MCG.FRDIV.scale, value: '32'}
|
||||
- {id: MCG.IREFS.sel, value: MCG.FRDIV}
|
||||
- {id: MCG.PLLS.sel, value: MCG.PLL}
|
||||
- {id: MCG.PRDIV.scale, value: '20', locked: true}
|
||||
- {id: MCG.VDIV.scale, value: '48', locked: true}
|
||||
- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
|
||||
- {id: MCG_C2_RANGE0_CFG, value: Very_high}
|
||||
- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
|
||||
- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
|
||||
- {id: RTCCLKOUTConfig, value: 'yes'}
|
||||
- {id: RTC_CR_OSCE_CFG, value: Enabled}
|
||||
- {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC10PF}
|
||||
- {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
|
||||
- {id: SIM.OUTDIV2.scale, value: '2'}
|
||||
- {id: SIM.OUTDIV3.scale, value: '3'}
|
||||
- {id: SIM.OUTDIV4.scale, value: '5'}
|
||||
- {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK}
|
||||
- {id: SIM.RTCCLKOUTSEL.sel, value: RTC.RTC32KCLK}
|
||||
- {id: SIM.SDHCSRCSEL.sel, value: OSC.OSCERCLK}
|
||||
- {id: SIM.TIMESRCSEL.sel, value: OSC.OSCERCLK}
|
||||
- {id: SIM.USBDIV.scale, value: '5'}
|
||||
- {id: SIM.USBFRAC.scale, value: '2'}
|
||||
- {id: SIM.USBSRCSEL.sel, value: SIM.USBDIV}
|
||||
sources:
|
||||
- {id: OSC.OSC.outFreq, value: 50 MHz, enabled: true}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
const mcg_config_t mcgConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
|
||||
.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
|
||||
.ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
|
||||
.fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
|
||||
.frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
|
||||
.drs = kMCG_DrsLow, /* Low frequency range */
|
||||
.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
|
||||
.oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
|
||||
.pll0Config =
|
||||
{
|
||||
.enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
|
||||
.prdiv = 0x13U, /* PLL Reference divider: divided by 20 */
|
||||
.vdiv = 0x18U, /* VCO divider: multiplied by 48 */
|
||||
},
|
||||
};
|
||||
const sim_clock_config_t simConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
|
||||
.er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
|
||||
.clkdiv1 = 0x1240000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /3, OUTDIV4: /5 */
|
||||
};
|
||||
const osc_config_t oscConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.freq = 50000000U, /* Oscillator frequency: 50000000Hz */
|
||||
.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
|
||||
.workMode = kOSC_ModeExt, /* Use external clock */
|
||||
.oscerConfig =
|
||||
{
|
||||
.enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
|
||||
}
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockRUN(void)
|
||||
{
|
||||
/* Set the system clock dividers in SIM to safe value. */
|
||||
CLOCK_SetSimSafeDivs();
|
||||
/* Initializes OSC0 according to board configuration. */
|
||||
CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
|
||||
CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
|
||||
/* Configure the Internal Reference clock (MCGIRCLK). */
|
||||
CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode,
|
||||
mcgConfig_BOARD_BootClockRUN.ircs,
|
||||
mcgConfig_BOARD_BootClockRUN.fcrdiv);
|
||||
/* Configure FLL external reference divider (FRDIV). */
|
||||
CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv);
|
||||
/* Set MCG to PEE mode. */
|
||||
CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockRUN.oscsel,
|
||||
kMCG_PllClkSelPll0,
|
||||
&mcgConfig_BOARD_BootClockRUN.pll0Config);
|
||||
/* Set the clock configuration in SIM module. */
|
||||
CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
|
||||
/* Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
********************* Configuration BOARD_BootClockVLPR ***********************
|
||||
******************************************************************************/
|
||||
/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockVLPR
|
||||
outputs:
|
||||
- {id: Bus_clock.outFreq, value: 4 MHz}
|
||||
- {id: Core_clock.outFreq, value: 4 MHz, locked: true, accuracy: '0.001'}
|
||||
- {id: Flash_clock.outFreq, value: 800 kHz}
|
||||
- {id: FlexBus_clock.outFreq, value: 4 MHz}
|
||||
- {id: LPO_clock.outFreq, value: 1 kHz}
|
||||
- {id: MCGIRCLK.outFreq, value: 4 MHz}
|
||||
- {id: System_clock.outFreq, value: 4 MHz}
|
||||
settings:
|
||||
- {id: MCGMode, value: BLPI}
|
||||
- {id: powerMode, value: VLPR}
|
||||
- {id: MCG.CLKS.sel, value: MCG.IRCS}
|
||||
- {id: MCG.FCRDIV.scale, value: '1'}
|
||||
- {id: MCG.FRDIV.scale, value: '32'}
|
||||
- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
|
||||
- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
|
||||
- {id: MCG_C2_RANGE0_CFG, value: Very_high}
|
||||
- {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high}
|
||||
- {id: RTC_CR_OSCE_CFG, value: Enabled}
|
||||
- {id: RTC_CR_OSC_CAP_LOAD_CFG, value: SC10PF}
|
||||
- {id: SIM.OSC32KSEL.sel, value: RTC.RTC32KCLK}
|
||||
- {id: SIM.OUTDIV3.scale, value: '1'}
|
||||
- {id: SIM.OUTDIV4.scale, value: '5'}
|
||||
- {id: SIM.PLLFLLSEL.sel, value: IRC48M.IRC48MCLK}
|
||||
- {id: SIM.RTCCLKOUTSEL.sel, value: RTC.RTC32KCLK}
|
||||
sources:
|
||||
- {id: OSC.OSC.outFreq, value: 50 MHz}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockVLPR configuration
|
||||
******************************************************************************/
|
||||
const mcg_config_t mcgConfig_BOARD_BootClockVLPR =
|
||||
{
|
||||
.mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */
|
||||
.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
|
||||
.ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
|
||||
.fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
|
||||
.frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
|
||||
.drs = kMCG_DrsLow, /* Low frequency range */
|
||||
.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
|
||||
.oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
|
||||
.pll0Config =
|
||||
{
|
||||
.enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
|
||||
.prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
|
||||
.vdiv = 0x0U, /* VCO divider: multiplied by 24 */
|
||||
},
|
||||
};
|
||||
const sim_clock_config_t simConfig_BOARD_BootClockVLPR =
|
||||
{
|
||||
.pllFllSel = SIM_PLLFLLSEL_IRC48MCLK_CLK, /* PLLFLL select: IRC48MCLK clock */
|
||||
.er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK, /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
|
||||
.clkdiv1 = 0x40000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV3: /1, OUTDIV4: /5 */
|
||||
};
|
||||
const osc_config_t oscConfig_BOARD_BootClockVLPR =
|
||||
{
|
||||
.freq = 0U, /* Oscillator frequency: 0Hz */
|
||||
.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
|
||||
.workMode = kOSC_ModeExt, /* Use external clock */
|
||||
.oscerConfig =
|
||||
{
|
||||
.enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
|
||||
}
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockVLPR configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockVLPR(void)
|
||||
{
|
||||
/* Set the system clock dividers in SIM to safe value. */
|
||||
CLOCK_SetSimSafeDivs();
|
||||
/* Set MCG to BLPI mode. */
|
||||
CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv,
|
||||
mcgConfig_BOARD_BootClockVLPR.ircs,
|
||||
mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
|
||||
/* Set the clock configuration in SIM module. */
|
||||
CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
|
||||
/* Set VLPR power mode. */
|
||||
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
|
||||
#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
|
||||
SMC_SetPowerModeVlpr(SMC, false);
|
||||
#else
|
||||
SMC_SetPowerModeVlpr(SMC);
|
||||
#endif
|
||||
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
|
||||
{
|
||||
}
|
||||
/* Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
|
||||
}
|
||||
|
||||
|
|
@ -1,112 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _CLOCK_CONFIG_H_
|
||||
#define _CLOCK_CONFIG_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#define BOARD_XTAL0_CLK_HZ 50000000U /*!< Board xtal0 frequency in Hz */
|
||||
|
||||
/*******************************************************************************
|
||||
********************** Configuration BOARD_BootClockRUN ***********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 120000000U /*!< Core clock frequency: 120000000Hz */
|
||||
|
||||
/*! @brief MCG set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const mcg_config_t mcgConfig_BOARD_BootClockRUN;
|
||||
/*! @brief SIM module set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const sim_clock_config_t simConfig_BOARD_BootClockRUN;
|
||||
/*! @brief OSC set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const osc_config_t oscConfig_BOARD_BootClockRUN;
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockRUN(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
********************* Configuration BOARD_BootClockVLPR ***********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockVLPR configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK 4000000U /*!< Core clock frequency: 4000000Hz */
|
||||
|
||||
/*! @brief MCG set for BOARD_BootClockVLPR configuration.
|
||||
*/
|
||||
extern const mcg_config_t mcgConfig_BOARD_BootClockVLPR;
|
||||
/*! @brief SIM module set for BOARD_BootClockVLPR configuration.
|
||||
*/
|
||||
extern const sim_clock_config_t simConfig_BOARD_BootClockVLPR;
|
||||
/*! @brief OSC set for BOARD_BootClockVLPR configuration.
|
||||
*/
|
||||
extern const osc_config_t oscConfig_BOARD_BootClockVLPR;
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockVLPR configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockVLPR(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
#endif /* _CLOCK_CONFIG_H_ */
|
||||
|
||||
|
|
@ -1,299 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* How to setup clock using clock driver functions:
|
||||
*
|
||||
* 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
|
||||
* and flash clock are in allowed range during clock mode switch.
|
||||
*
|
||||
* 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
|
||||
*
|
||||
* 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
|
||||
* internal reference clock(MCGIRCLK). Follow the steps to setup:
|
||||
*
|
||||
* 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
|
||||
*
|
||||
* 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
|
||||
* correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
|
||||
* explicitly to setup MCGIRCLK.
|
||||
*
|
||||
* 3). Don't need to configure FLL explicitly, because if target mode is FLL
|
||||
* mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
|
||||
* if the target mode is not FLL mode, the FLL is disabled.
|
||||
*
|
||||
* 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
|
||||
* setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
|
||||
* be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
|
||||
*
|
||||
* 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
|
||||
*/
|
||||
|
||||
/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
|
||||
!!ClocksProfile
|
||||
product: Clocks v1.0
|
||||
processor: MKL25Z128xxx4
|
||||
package_id: MKL25Z128VLK4
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 1.1.0
|
||||
board: FRDM-KL25Z
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
|
||||
|
||||
#include "fsl_smc.h"
|
||||
#include "clock_config.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#define MCG_PLL_DISABLE 0U /*!< MCGPLLCLK disabled */
|
||||
#define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */
|
||||
#define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */
|
||||
#define SIM_OSC32KSEL_LPO_CLK 3U /*!< OSC32KSEL select: LPO clock */
|
||||
#define SIM_PLLFLLSEL_MCGFLLCLK_CLK 0U /*!< PLLFLL select: MCGFLLCLK clock */
|
||||
#define SIM_PLLFLLSEL_MCGPLLCLK_CLK 1U /*!< PLLFLL select: MCGPLLCLK clock */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/* System clock frequency. */
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
/*FUNCTION**********************************************************************
|
||||
*
|
||||
* Function Name : CLOCK_CONFIG_SetFllExtRefDiv
|
||||
* Description : Configure FLL external reference divider (FRDIV).
|
||||
* Param frdiv : The value to set FRDIV.
|
||||
*
|
||||
*END**************************************************************************/
|
||||
static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)
|
||||
{
|
||||
MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
********************** Configuration BOARD_BootClockRUN ***********************
|
||||
******************************************************************************/
|
||||
/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockRUN
|
||||
outputs:
|
||||
- {id: Bus_clock.outFreq, value: 24 MHz}
|
||||
- {id: Core_clock.outFreq, value: 48 MHz, locked: true, accuracy: '0.001'}
|
||||
- {id: ERCLK32K.outFreq, value: 1 kHz}
|
||||
- {id: Flash_clock.outFreq, value: 24 MHz}
|
||||
- {id: LPO_clock.outFreq, value: 1 kHz}
|
||||
- {id: MCGIRCLK.outFreq, value: 32.768 kHz}
|
||||
- {id: OSCERCLK.outFreq, value: 8 MHz}
|
||||
- {id: PLLFLLCLK.outFreq, value: 48 MHz}
|
||||
- {id: System_clock.outFreq, value: 48 MHz}
|
||||
settings:
|
||||
- {id: MCGMode, value: PEE}
|
||||
- {id: MCG.FCRDIV.scale, value: '1', locked: true}
|
||||
- {id: MCG.FRDIV.scale, value: '32'}
|
||||
- {id: MCG.IREFS.sel, value: MCG.FRDIV}
|
||||
- {id: MCG.PLLS.sel, value: MCG.PLL}
|
||||
- {id: MCG.PRDIV.scale, value: '2', locked: true}
|
||||
- {id: MCG.VDIV.scale, value: '24', locked: true}
|
||||
- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
|
||||
- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
|
||||
- {id: MCG_C2_RANGE0_CFG, value: High}
|
||||
- {id: MCG_C2_RANGE0_FRDIV_CFG, value: High}
|
||||
- {id: OSC0_CR_ERCLKEN_CFG, value: Enabled}
|
||||
- {id: OSC_CR_ERCLKEN_CFG, value: Enabled}
|
||||
- {id: SIM.CLKOUTSEL.sel, value: SIM.OUTDIV4}
|
||||
- {id: SIM.OSC32KSEL.sel, value: PMC.LPOCLK}
|
||||
- {id: SIM.OUTDIV1.scale, value: '2'}
|
||||
- {id: SIM.PLLFLLSEL.sel, value: SIM.MCGPLLCLK_DIV2}
|
||||
- {id: SIM.TPMSRCSEL.sel, value: SIM.PLLFLLSEL}
|
||||
- {id: SIM.UART0SRCSEL.sel, value: SIM.PLLFLLSEL}
|
||||
- {id: SIM.USBSRCSEL.sel, value: SIM.PLLFLLSEL}
|
||||
sources:
|
||||
- {id: OSC.OSC.outFreq, value: 8 MHz, enabled: true}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
const mcg_config_t mcgConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */
|
||||
.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
|
||||
.ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
|
||||
.fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
|
||||
.frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
|
||||
.drs = kMCG_DrsLow, /* Low frequency range */
|
||||
.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
|
||||
.pll0Config =
|
||||
{
|
||||
.enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
|
||||
.prdiv = 0x1U, /* PLL Reference divider: divided by 2 */
|
||||
.vdiv = 0x0U, /* VCO divider: multiplied by 24 */
|
||||
},
|
||||
};
|
||||
const sim_clock_config_t simConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
|
||||
.er32kSrc = SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */
|
||||
.clkdiv1 = 0x10010000U, /* SIM_CLKDIV1 - OUTDIV1: /2, OUTDIV4: /2 */
|
||||
};
|
||||
const osc_config_t oscConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.freq = 8000000U, /* Oscillator frequency: 8000000Hz */
|
||||
.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
|
||||
.workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
|
||||
.oscerConfig =
|
||||
{
|
||||
.enableMode = kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
|
||||
}
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockRUN(void)
|
||||
{
|
||||
/* Set the system clock dividers in SIM to safe value. */
|
||||
CLOCK_SetSimSafeDivs();
|
||||
/* Initializes OSC0 according to board configuration. */
|
||||
CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
|
||||
CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
|
||||
/* Configure FLL external reference divider (FRDIV). */
|
||||
CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockRUN.frdiv);
|
||||
/* Set MCG to PEE mode. */
|
||||
CLOCK_BootToPeeMode(kMCG_OscselOsc,
|
||||
kMCG_PllClkSelPll0,
|
||||
&mcgConfig_BOARD_BootClockRUN.pll0Config);
|
||||
/* Configure the Internal Reference clock (MCGIRCLK). */
|
||||
CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode,
|
||||
mcgConfig_BOARD_BootClockRUN.ircs,
|
||||
mcgConfig_BOARD_BootClockRUN.fcrdiv);
|
||||
/* Set the clock configuration in SIM module. */
|
||||
CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
|
||||
/* Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
********************* Configuration BOARD_BootClockVLPR ***********************
|
||||
******************************************************************************/
|
||||
/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockVLPR
|
||||
outputs:
|
||||
- {id: Bus_clock.outFreq, value: 800 kHz}
|
||||
- {id: Core_clock.outFreq, value: 4 MHz}
|
||||
- {id: ERCLK32K.outFreq, value: 1 kHz}
|
||||
- {id: Flash_clock.outFreq, value: 800 kHz}
|
||||
- {id: LPO_clock.outFreq, value: 1 kHz}
|
||||
- {id: MCGIRCLK.outFreq, value: 4 MHz}
|
||||
- {id: System_clock.outFreq, value: 4 MHz}
|
||||
settings:
|
||||
- {id: MCGMode, value: BLPI}
|
||||
- {id: powerMode, value: VLPR}
|
||||
- {id: MCG.CLKS.sel, value: MCG.IRCS}
|
||||
- {id: MCG.FCRDIV.scale, value: '1', locked: true}
|
||||
- {id: MCG.FRDIV.scale, value: '32'}
|
||||
- {id: MCG.IRCS.sel, value: MCG.FCRDIV}
|
||||
- {id: MCG_C1_IRCLKEN_CFG, value: Enabled}
|
||||
- {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower}
|
||||
- {id: MCG_C2_RANGE0_CFG, value: High}
|
||||
- {id: MCG_C2_RANGE0_FRDIV_CFG, value: High}
|
||||
- {id: SIM.OSC32KSEL.sel, value: PMC.LPOCLK}
|
||||
- {id: SIM.OUTDIV4.scale, value: '5'}
|
||||
sources:
|
||||
- {id: OSC.OSC.outFreq, value: 8 MHz}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockVLPR configuration
|
||||
******************************************************************************/
|
||||
const mcg_config_t mcgConfig_BOARD_BootClockVLPR =
|
||||
{
|
||||
.mcgMode = kMCG_ModeBLPI, /* BLPI - Bypassed Low Power Internal */
|
||||
.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enabled, MCGIRCLK disabled in STOP mode */
|
||||
.ircs = kMCG_IrcFast, /* Fast internal reference clock selected */
|
||||
.fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */
|
||||
.frdiv = 0x0U, /* FLL reference clock divider: divided by 32 */
|
||||
.drs = kMCG_DrsLow, /* Low frequency range */
|
||||
.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
|
||||
.pll0Config =
|
||||
{
|
||||
.enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
|
||||
.prdiv = 0x0U, /* PLL Reference divider: divided by 1 */
|
||||
.vdiv = 0x0U, /* VCO divider: multiplied by 24 */
|
||||
},
|
||||
};
|
||||
const sim_clock_config_t simConfig_BOARD_BootClockVLPR =
|
||||
{
|
||||
.pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
|
||||
.er32kSrc = SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */
|
||||
.clkdiv1 = 0x40000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV4: /5 */
|
||||
};
|
||||
const osc_config_t oscConfig_BOARD_BootClockVLPR =
|
||||
{
|
||||
.freq = 0U, /* Oscillator frequency: 0Hz */
|
||||
.capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
|
||||
.workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
|
||||
.oscerConfig =
|
||||
{
|
||||
.enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
|
||||
}
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockVLPR configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockVLPR(void)
|
||||
{
|
||||
/* Set the system clock dividers in SIM to safe value. */
|
||||
CLOCK_SetSimSafeDivs();
|
||||
/* Set MCG to BLPI mode. */
|
||||
CLOCK_BootToBlpiMode(mcgConfig_BOARD_BootClockVLPR.fcrdiv,
|
||||
mcgConfig_BOARD_BootClockVLPR.ircs,
|
||||
mcgConfig_BOARD_BootClockVLPR.irclkEnableMode);
|
||||
/* Set the clock configuration in SIM module. */
|
||||
CLOCK_SetSimConfig(&simConfig_BOARD_BootClockVLPR);
|
||||
/* Set VLPR power mode. */
|
||||
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
|
||||
#if (defined(FSL_FEATURE_SMC_HAS_LPWUI) && FSL_FEATURE_SMC_HAS_LPWUI)
|
||||
SMC_SetPowerModeVlpr(SMC, false);
|
||||
#else
|
||||
SMC_SetPowerModeVlpr(SMC);
|
||||
#endif
|
||||
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
|
||||
{
|
||||
}
|
||||
/* Set SystemCoreClock variable. */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
|
||||
}
|
||||
|
||||
|
|
@ -1,112 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _CLOCK_CONFIG_H_
|
||||
#define _CLOCK_CONFIG_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#define BOARD_XTAL0_CLK_HZ 8000000U /*!< Board xtal0 frequency in Hz */
|
||||
|
||||
/*******************************************************************************
|
||||
********************** Configuration BOARD_BootClockRUN ***********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
|
||||
|
||||
/*! @brief MCG set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const mcg_config_t mcgConfig_BOARD_BootClockRUN;
|
||||
/*! @brief SIM module set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const sim_clock_config_t simConfig_BOARD_BootClockRUN;
|
||||
/*! @brief OSC set for BOARD_BootClockRUN configuration.
|
||||
*/
|
||||
extern const osc_config_t oscConfig_BOARD_BootClockRUN;
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockRUN(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
********************* Configuration BOARD_BootClockVLPR ***********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockVLPR configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKVLPR_CORE_CLOCK 4000000U /*!< Core clock frequency: 4000000Hz */
|
||||
|
||||
/*! @brief MCG set for BOARD_BootClockVLPR configuration.
|
||||
*/
|
||||
extern const mcg_config_t mcgConfig_BOARD_BootClockVLPR;
|
||||
/*! @brief SIM module set for BOARD_BootClockVLPR configuration.
|
||||
*/
|
||||
extern const sim_clock_config_t simConfig_BOARD_BootClockVLPR;
|
||||
/*! @brief OSC set for BOARD_BootClockVLPR configuration.
|
||||
*/
|
||||
extern const osc_config_t oscConfig_BOARD_BootClockVLPR;
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockVLPR configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockVLPR(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
#endif /* _CLOCK_CONFIG_H_ */
|
||||
|
||||
|
|
@ -1,221 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_smc.h"
|
||||
#include "clock_config.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
/*! @brief Clock configuration structure. */
|
||||
typedef struct _clock_config
|
||||
{
|
||||
mcg_config_t mcgConfig; /*!< MCG configuration. */
|
||||
sim_clock_config_t simConfig; /*!< SIM configuration. */
|
||||
osc_config_t oscConfig; /*!< OSC configuration. */
|
||||
uint32_t coreClock; /*!< core clock frequency. */
|
||||
} clock_config_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/* System clock frequency. */
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/* Configuration for enter VLPR mode. Core clock = 4MHz. */
|
||||
const clock_config_t g_defaultClockConfigVlpr = {
|
||||
.mcgConfig =
|
||||
{
|
||||
.mcgMode = kMCG_ModeBLPI, /* Work in BLPI mode. */
|
||||
.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
|
||||
.ircs = kMCG_IrcFast, /* Select IRC4M. */
|
||||
.fcrdiv = 0U, /* FCRDIV is 0. */
|
||||
|
||||
.frdiv = 5U,
|
||||
.drs = kMCG_DrsLow, /* Low frequency range */
|
||||
.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
|
||||
.oscsel = kMCG_OscselOsc, /* Select OSC */
|
||||
},
|
||||
.simConfig =
|
||||
{
|
||||
.er32kSrc = 0U, /* ERCLK32K selection, use OSC. */
|
||||
.clkdiv1 = 0x00040000U, /* SIM_CLKDIV1. */
|
||||
},
|
||||
.oscConfig =
|
||||
{
|
||||
.freq = BOARD_XTAL0_CLK_HZ, /* Feed by RF XTAL_32M */
|
||||
.workMode = kOSC_ModeExt, /* Must work in external source mode. */
|
||||
},
|
||||
.coreClock = 4000000U, /* Core clock frequency */
|
||||
};
|
||||
|
||||
/* Configuration for enter RUN mode. Core clock = 40MHz. */
|
||||
const clock_config_t g_defaultClockConfigRun = {
|
||||
.mcgConfig =
|
||||
{
|
||||
.mcgMode = kMCG_ModeFEE, /* Work in FEE mode. */
|
||||
.irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
|
||||
.ircs = kMCG_IrcSlow, /* Select IRC32k. */
|
||||
.fcrdiv = 0U, /* FCRDIV is 0. */
|
||||
|
||||
.frdiv = 5U,
|
||||
.drs = kMCG_DrsMid, /* Middle frequency range */
|
||||
.dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
|
||||
.oscsel = kMCG_OscselOsc, /* Select OSC */
|
||||
},
|
||||
.simConfig =
|
||||
{
|
||||
.er32kSrc = 0U, /* ERCLK32K selection, use OSC. */
|
||||
.clkdiv1 = 0x00010000U, /* SIM_CLKDIV1. */
|
||||
},
|
||||
.oscConfig =
|
||||
{
|
||||
.freq = BOARD_XTAL0_CLK_HZ, /* Feed by RF XTAL_32M */
|
||||
.workMode = kOSC_ModeExt, /* Must work in external source mode. */
|
||||
},
|
||||
.coreClock = 40000000U, /* Core clock frequency */
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
/*
|
||||
* How to setup clock using clock driver functions:
|
||||
*
|
||||
* 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
|
||||
* and flash clock are in allowed range during clock mode switch.
|
||||
*
|
||||
* 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
|
||||
*
|
||||
* 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
|
||||
* internal reference clock(MCGIRCLK). Follow the steps to setup:
|
||||
*
|
||||
* 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
|
||||
*
|
||||
* 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
|
||||
* correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
|
||||
* explicitly to setup MCGIRCLK.
|
||||
*
|
||||
* 3). Don't need to configure FLL explicitly, because if target mode is FLL
|
||||
* mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
|
||||
* if the target mode is not FLL mode, the FLL is disabled.
|
||||
*
|
||||
* 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
|
||||
* setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
|
||||
* be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
|
||||
*
|
||||
* 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
|
||||
*/
|
||||
|
||||
static void CLOCK_SYS_FllStableDelay(void)
|
||||
{
|
||||
uint32_t i = 30000U;
|
||||
while (i--)
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
void BOARD_BootClockVLPR(void)
|
||||
{
|
||||
/* ERR010224 */
|
||||
RSIM->RF_OSC_CTRL |= RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK; /* Prevent XTAL_OUT_EN from generating XTAL_OUT request */
|
||||
|
||||
CLOCK_SetSimSafeDivs();
|
||||
|
||||
CLOCK_BootToBlpiMode(g_defaultClockConfigVlpr.mcgConfig.fcrdiv, g_defaultClockConfigVlpr.mcgConfig.ircs,
|
||||
g_defaultClockConfigVlpr.mcgConfig.irclkEnableMode);
|
||||
|
||||
CLOCK_SetSimConfig(&g_defaultClockConfigVlpr.simConfig);
|
||||
|
||||
SystemCoreClock = g_defaultClockConfigVlpr.coreClock;
|
||||
|
||||
SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
|
||||
SMC_SetPowerModeVlpr(SMC);
|
||||
while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
void BOARD_BootClockRUN(void)
|
||||
{
|
||||
BOARD_RfOscInit();
|
||||
|
||||
CLOCK_SetSimSafeDivs();
|
||||
|
||||
CLOCK_InitOsc0(&g_defaultClockConfigRun.oscConfig);
|
||||
CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
|
||||
CLOCK_BootToFeeMode(kMCG_OscselOsc, g_defaultClockConfigRun.mcgConfig.frdiv,
|
||||
g_defaultClockConfigRun.mcgConfig.dmx32, g_defaultClockConfigRun.mcgConfig.drs,
|
||||
CLOCK_SYS_FllStableDelay);
|
||||
|
||||
CLOCK_SetInternalRefClkConfig(g_defaultClockConfigRun.mcgConfig.irclkEnableMode,
|
||||
g_defaultClockConfigRun.mcgConfig.ircs, g_defaultClockConfigRun.mcgConfig.fcrdiv);
|
||||
|
||||
CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig);
|
||||
|
||||
SystemCoreClock = g_defaultClockConfigRun.coreClock;
|
||||
}
|
||||
|
||||
void BOARD_RfOscInit(void)
|
||||
{
|
||||
uint32_t temp, tempTrim;
|
||||
uint8_t revId;
|
||||
|
||||
/* Obtain REV ID from SIM */
|
||||
temp = SIM->SDID;
|
||||
revId = (uint8_t)((temp & SIM_SDID_REVID_MASK) >> SIM_SDID_REVID_SHIFT);
|
||||
|
||||
if(0 == revId)
|
||||
{
|
||||
tempTrim = RSIM->ANA_TRIM;
|
||||
RSIM->ANA_TRIM |= RSIM_ANA_TRIM_BB_LDO_XO_TRIM_MASK; /* Set max trim for BB LDO for XO */
|
||||
}/* Workaround for Rev 1.0 XTAL startup and ADC analog diagnostics circuitry */
|
||||
|
||||
/* Turn on clocks for the XCVR */
|
||||
/* Enable RF OSC in RSIM and wait for ready */
|
||||
temp = RSIM->CONTROL;
|
||||
temp &= ~RSIM_CONTROL_RF_OSC_EN_MASK;
|
||||
RSIM->CONTROL = temp | RSIM_CONTROL_RF_OSC_EN(1);
|
||||
|
||||
/* ERR010224 */
|
||||
RSIM->RF_OSC_CTRL |= RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK; /* Prevent XTAL_OUT_EN from generating XTAL_OUT request */
|
||||
|
||||
while((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) == 0); /* Wait for RF_OSC_READY */
|
||||
|
||||
if(0 == revId)
|
||||
{
|
||||
SIM->SCGC5 |= SIM_SCGC5_PHYDIG_MASK;
|
||||
XCVR_TSM->OVRD0 |= XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_EN_MASK | XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_MASK; /* Force ADC DAC LDO on to prevent BGAP failure */
|
||||
|
||||
RSIM->ANA_TRIM = tempTrim; /* Reset LDO trim settings */
|
||||
}/* Workaround for Rev 1.0 XTAL startup and ADC analog diagnostics circuitry */
|
||||
}
|
||||
|
|
@ -1,55 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _CLOCK_CONFIG_H_
|
||||
#define _CLOCK_CONFIG_H_
|
||||
|
||||
/*******************************************************************************
|
||||
* DEFINITION
|
||||
******************************************************************************/
|
||||
#define BOARD_XTAL0_CLK_HZ 32000000U
|
||||
#define BOARD_XTAL32K_CLK_HZ 32768U
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
void BOARD_BootClockVLPR(void);
|
||||
void BOARD_BootClockRUN(void);
|
||||
void BOARD_RfOscInit(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
#endif /* _CLOCK_CONFIG_H_ */
|
||||
Loading…
Reference in a new issue