arch: arm: cortex_m: Convert cpu_idle from ASM to C
Asm is notoriously harder to maintain than C and requires core specific adaptation which impairs even more the readability of the code. This change reduces the need for core specific conditional compilation and unifies irq locking code. Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com> # Conflicts: # soc/arm/nordic_nrf/nrf53/soc_cpu_idle.h
This commit is contained in:
Wilfried Chauveau
Carles Cufí
parent
f11027df80
commit
4760aad353
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@ -16,7 +16,7 @@ zephyr_library_sources(
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irq_manage.c
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prep_c.c
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thread.c
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cpu_idle.S
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cpu_idle.c
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)
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zephyr_library_sources_ifndef(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER irq_init.c)
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@ -1,201 +0,0 @@
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/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief ARM Cortex-M power management
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*
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*/
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#include <zephyr/toolchain.h>
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#include <zephyr/linker/sections.h>
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#if defined(CONFIG_ARM_ON_EXIT_CPU_IDLE)
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#include <soc_cpu_idle.h>
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#endif
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_ASM_FILE_PROLOGUE
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GTEXT(z_arm_cpu_idle_init)
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GTEXT(arch_cpu_idle)
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GTEXT(arch_cpu_atomic_idle)
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#define _SCB_SCR 0xE000ED10
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#define _SCB_SCR_SEVONPEND (1 << 4)
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#define _SCB_SCR_SLEEPDEEP (1 << 2)
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#define _SCB_SCR_SLEEPONEXIT (1 << 1)
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#define _SCR_INIT_BITS _SCB_SCR_SEVONPEND
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.macro _sleep_if_allowed wait_instruction
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#if defined(CONFIG_ARM_ON_ENTER_CPU_IDLE_HOOK)
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push {r0, lr}
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bl z_arm_on_enter_cpu_idle
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/* Skip the wait instruction if on_enter_cpu_idle() returns false. */
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cmp r0, #0
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beq _skip_\@
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#endif /* CONFIG_ARM_ON_ENTER_CPU_IDLE_HOOK */
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/*
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* Wait for all memory transactions to complete before entering low
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* power state.
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*/
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dsb
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\wait_instruction
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#if defined(CONFIG_ARM_ON_EXIT_CPU_IDLE)
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/* Inline the macro provided by SoC-specific code */
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SOC_ON_EXIT_CPU_IDLE
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#endif /* CONFIG_ARM_ON_EXIT_CPU_IDLE */
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#if defined(CONFIG_ARM_ON_ENTER_CPU_IDLE_HOOK)
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_skip_\@:
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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pop {r0, r1}
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mov lr, r1
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#else
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pop {r0, lr}
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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#endif /* CONFIG_ARM_ON_ENTER_CPU_IDLE_HOOK */
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.endm
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/**
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*
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* @brief Initialization of CPU idle
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*
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* Only called by arch_kernel_init(). Sets SEVONPEND bit once for the system's
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* duration.
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*
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* C function prototype:
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*
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* void z_arm_cpu_idle_init(void);
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*/
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SECTION_FUNC(TEXT, z_arm_cpu_idle_init)
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ldr r1, =_SCB_SCR
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movs.n r2, #_SCR_INIT_BITS
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str r2, [r1]
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bx lr
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SECTION_FUNC(TEXT, arch_cpu_idle)
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#if defined(CONFIG_TRACING) || \
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defined(CONFIG_ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK)
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push {r0, lr}
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#ifdef CONFIG_TRACING
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bl sys_trace_idle
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#endif
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#ifdef CONFIG_ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK
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bl z_arm_on_enter_cpu_idle_prepare
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#endif
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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pop {r0, r1}
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mov lr, r1
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#else
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pop {r0, lr}
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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#endif
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#if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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/*
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* PRIMASK is always cleared on ARMv7-M and ARMv8-M Mainline (not used
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* for interrupt locking), and configuring BASEPRI to the lowest
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* priority to ensure wake-up will cause interrupts to be serviced
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* before entering low power state.
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*
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* Set PRIMASK before configuring BASEPRI to prevent interruption
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* before wake-up.
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*/
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cpsid i
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/*
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* Set wake-up interrupt priority to the lowest and synchronise to
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* ensure that this is visible to the WFI instruction.
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*/
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eors.n r0, r0
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msr BASEPRI, r0
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isb
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#else
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/*
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* For all the other ARM architectures that do not implement BASEPRI,
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* PRIMASK is used as the interrupt locking mechanism, and it is not
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* necessary to set PRIMASK here, as PRIMASK would have already been
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* set by the caller as part of interrupt locking if necessary
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* (i.e. if the caller sets _kernel.idle).
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*/
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#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
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/* Enter low power state */
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_sleep_if_allowed wfi
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/*
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* Clear PRIMASK and flush instruction buffer to immediately service
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* the wake-up interrupt.
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*/
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cpsie i
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isb
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bx lr
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SECTION_FUNC(TEXT, arch_cpu_atomic_idle)
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#if defined(CONFIG_TRACING) || \
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defined(CONFIG_ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK)
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push {r0, lr}
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#ifdef CONFIG_TRACING
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bl sys_trace_idle
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#endif
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#ifdef CONFIG_ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK
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bl z_arm_on_enter_cpu_idle_prepare
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#endif
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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pop {r0, r1}
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mov lr, r1
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#else
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pop {r0, lr}
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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#endif
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/*
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* Lock PRIMASK while sleeping: wfe will still get interrupted by
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* incoming interrupts but the CPU will not service them right away.
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*/
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cpsid i
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/*
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* No need to set SEVONPEND, it's set once in z_arm_cpu_idle_init()
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* and never touched again.
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*/
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/* r0: interrupt mask from caller */
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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/* No BASEPRI, call wfe directly
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* (SEVONPEND is set in z_arm_cpu_idle_init())
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*/
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_sleep_if_allowed wfe
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cmp r0, #0
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bne _irq_disabled
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cpsie i
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_irq_disabled:
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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/* r1: zero, for setting BASEPRI (needs a register) */
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eors.n r1, r1
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/* unlock BASEPRI so wfe gets interrupted by incoming interrupts */
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msr BASEPRI, r1
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_sleep_if_allowed wfe
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msr BASEPRI, r0
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cpsie i
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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bx lr
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128
arch/arm/core/cortex_m/cpu_idle.c
Normal file
128
arch/arm/core/cortex_m/cpu_idle.c
Normal file
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@ -0,0 +1,128 @@
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/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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* Copyright (c) 2023 Arm Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief ARM Cortex-M power management
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*/
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#include <zephyr/kernel.h>
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#include <cmsis_core.h>
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#if defined(CONFIG_ARM_ON_EXIT_CPU_IDLE)
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#include <soc_cpu_idle.h>
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#endif
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/**
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* @brief Initialization of CPU idle
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*
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* Only called by arch_kernel_init(). Sets SEVONPEND bit once for the system's
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* duration.
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*/
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void z_arm_cpu_idle_init(void)
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{
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SCB->SCR = SCB_SCR_SEVONPEND_Msk;
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}
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#if defined(CONFIG_ARM_ON_EXIT_CPU_IDLE)
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#define ON_EXIT_IDLE_HOOK SOC_ON_EXIT_CPU_IDLE
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#else
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#define ON_EXIT_IDLE_HOOK do {} while (false)
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#endif
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#if defined(CONFIG_ARM_ON_ENTER_CPU_IDLE_HOOK)
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#define SLEEP_IF_ALLOWED(wait_instr) do { \
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if (!z_arm_on_enter_cpu_idle()) { \
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__DSB(); \
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wait_instr(); \
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ON_EXIT_IDLE_HOOK; \
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} \
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} while (false)
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#else
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#define SLEEP_IF_ALLOWED(wait_instr) do { \
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__DSB(); \
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wait_instr(); \
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ON_EXIT_IDLE_HOOK; \
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} while (false)
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#endif
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void arch_cpu_idle(void)
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{
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#if defined(CONFIG_TRACING)
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sys_trace_idle();
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#endif
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#if CONFIG_ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK
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z_arm_on_enter_cpu_idle_prepare();
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#endif
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#if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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/*
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* PRIMASK is always cleared on ARMv7-M and ARMv8-M (not used
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* for interrupt locking), and configuring BASEPRI to the lowest
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* priority to ensure wake-up will cause interrupts to be serviced
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* before entering low power state.
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*
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* Set PRIMASK before configuring BASEPRI to prevent interruption
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* before wake-up.
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*/
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__disable_irq();
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/*
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* Set wake-up interrupt priority to the lowest and synchronise to
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* ensure that this is visible to the WFI instruction.
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*/
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__set_BASEPRI(0);
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__ISB();
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#else
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/*
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* For all the other ARM architectures that do not implement BASEPRI,
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* PRIMASK is used as the interrupt locking mechanism, and it is not
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* necessary to set PRIMASK here, as PRIMASK would have already been
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* set by the caller as part of interrupt locking if necessary
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* (i.e. if the caller sets _kernel.idle).
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*/
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#endif
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/*
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* Wait for all memory transactions to complete before entering low
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* power state.
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*/
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SLEEP_IF_ALLOWED(__WFI);
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__enable_irq();
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__ISB();
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}
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void arch_cpu_atomic_idle(unsigned int key)
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{
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#if defined(CONFIG_TRACING)
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sys_trace_idle();
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#endif
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#if CONFIG_ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK
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z_arm_on_enter_cpu_idle_prepare();
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#endif
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/*
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* Lock PRIMASK while sleeping: wfe will still get interrupted by
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* incoming interrupts but the CPU will not service them right away.
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*/
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__disable_irq();
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/*
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* No need to set SEVONPEND, it's set once in z_arm_cpu_idle_init()
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* and never touched again.
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*/
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/*
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* Wait for all memory transactions to complete before entering low
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* power state.
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*/
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SLEEP_IF_ALLOWED(__WFE);
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arch_irq_unlock(key);
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}
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@ -8,19 +8,22 @@
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* @file SoC extensions of cpu_idle.S for the Nordic Semiconductor nRF53 processors family.
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*/
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#if defined(_ASMLANGUAGE)
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#define SOC_ON_EXIT_CPU_IDLE_4 \
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__NOP(); \
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__NOP(); \
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__NOP(); \
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__NOP();
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#define SOC_ON_EXIT_CPU_IDLE_8 \
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SOC_ON_EXIT_CPU_IDLE_4 \
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SOC_ON_EXIT_CPU_IDLE_4
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#if defined(CONFIG_SOC_NRF53_ANOMALY_168_WORKAROUND_FOR_EXECUTION_FROM_RAM)
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#define SOC_ON_EXIT_CPU_IDLE \
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.rept 26; \
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nop; \
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.endr
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SOC_ON_EXIT_CPU_IDLE_8; \
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SOC_ON_EXIT_CPU_IDLE_8; \
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SOC_ON_EXIT_CPU_IDLE_8; \
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__NOP(); \
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__NOP();
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#elif defined(CONFIG_SOC_NRF53_ANOMALY_168_WORKAROUND)
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#define SOC_ON_EXIT_CPU_IDLE \
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.rept 8; \
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nop; \
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.endr
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#define SOC_ON_EXIT_CPU_IDLE SOC_ON_EXIT_CPU_IDLE_8
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#endif
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#endif /* _ASMLANGUAGE */
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