intel_s1000: uart: configure UART for intel_s1000
intel_s1000 uses DesignWare IP for UART. National Semiconductor 16550 (UART) component specification is followed in this IP. Change-Id: Ied7df1dc178d55b6dbe71d729d6383ba07274ea4 Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
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15
arch/xtensa/soc/intel_s1000/soc.h
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15
arch/xtensa/soc/intel_s1000/soc.h
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@ -0,0 +1,15 @@
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/*
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* Copyright (c) 2017 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __INC_SOC_H
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#define __INC_SOC_H
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/*
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* UART - UART0
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*/
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#define UART_NS16550_PORT_0_BASE_ADDR 0x00080800
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#define UART_NS16550_PORT_0_CLK_FREQ 38400000
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#endif /* __INC_SOC_H */
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@ -10,4 +10,22 @@ config BOARD
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config BOARD_XTENSA
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def_bool y
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if UART_NS16550
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config UART_NS16550_PORT_0
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def_bool y
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if UART_NS16550_PORT_0
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config UART_NS16550_PORT_0_NAME
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default "UART_0"
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config UART_NS16550_PORT_0_BAUD_RATE
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default 115200
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config UART_NS16550_PORT_0_OPTIONS
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default 0
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endif # UART_NS16550_PORT_0
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endif # UART_NS16550
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endif # BOARD_INTEL_S1000_CRB
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boards/xtensa/intel_s1000_crb/board.h
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boards/xtensa/intel_s1000_crb/board.h
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/*
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* Copyright (c) 2017 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __INC_BOARD_H
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#define __INC_BOARD_H
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#include <soc.h>
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#endif /* __INC_BOARD_H */
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@ -13,3 +13,9 @@ CONFIG_GEN_IRQ_VECTOR_TABLE=n
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CONFIG_XTENSA_RESET_VECTOR=y
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CONFIG_XTENSA_USE_CORE_CRT1=y
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CONFIG_CONSOLE=y
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CONFIG_SERIAL_HAS_DRIVER=y
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CONFIG_SERIAL=y
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CONFIG_UART_CONSOLE=y
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CONFIG_UART_NS16550=y
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@ -23,6 +23,15 @@ static ALWAYS_INLINE void sys_write32(u32_t data, mem_addr_t addr)
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*(volatile u32_t *)addr = data;
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}
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static ALWAYS_INLINE u8_t sys_read8(mem_addr_t addr)
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{
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return *(volatile u8_t *)addr;
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}
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static ALWAYS_INLINE void sys_write8(u8_t data, mem_addr_t addr)
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{
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*(volatile u8_t *)addr = data;
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}
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/* Memory bit manipulation functions */
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