diff --git a/soc/riscv/andes_v5/ae350/soc.h b/soc/riscv/andes_v5/ae350/soc.h
deleted file mode 100644
index 07d8c69882..0000000000
--- a/soc/riscv/andes_v5/ae350/soc.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (c) 2021 Andes Technology Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @brief Macros for the Andes AE350 platform
- */
-
-#ifndef __RISCV_ANDES_AE350_SOC_H_
-#define __RISCV_ANDES_AE350_SOC_H_
-
-#endif /* __RISCV_ANDES_AE350_SOC_H_ */
diff --git a/soc/riscv/efinix_sapphire/soc.h b/soc/riscv/efinix_sapphire/soc.h
deleted file mode 100644
index 5530af1672..0000000000
--- a/soc/riscv/efinix_sapphire/soc.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (c) 2023 Efinix Inc.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef __RISCV32_EFINIX_SAPPHIRE_SOC_H_
-#define __RISCV32_EFINIX_SAPPHIRE_SOC_H_
-
-#include <zephyr/arch/riscv/sys_io.h>
-#include <zephyr/devicetree.h>
-
-#ifndef _ASMLANGUAGE
-
-#endif /* _ASMLANGUAGE */
-
-#endif /* __RISCV32_EFINIX_SAPPHIRE_SOC_H_ */
diff --git a/soc/riscv/gd_gd32/gd32vf103/soc.h b/soc/riscv/gd_gd32/gd32vf103/soc.h
deleted file mode 100644
index ad2add6fa8..0000000000
--- a/soc/riscv/gd_gd32/gd32vf103/soc.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @file SoC configuration macros for the GigaDevice GD32VF103 processor
- */
-
-#ifndef RISCV_GD32VF103_SOC_H_
-#define RISCV_GD32VF103_SOC_H_
-
-#endif  /* RISCV_GD32VF103_SOC_H */
diff --git a/soc/riscv/intel_niosv/niosv/soc.h b/soc/riscv/intel_niosv/niosv/soc.h
deleted file mode 100644
index 87458c91df..0000000000
--- a/soc/riscv/intel_niosv/niosv/soc.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Copyright (C) 2023, Intel Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef RISCV_INTEL_FPGA_NIOSV_H
-#define RISCV_INTEL_FPGA_NIOSV_H
-
-#include <zephyr/devicetree.h>
-
-#endif /* RISCV_INTEL_FPGA_NIOSV_H */
diff --git a/soc/riscv/microchip_miv/miv/soc.h b/soc/riscv/microchip_miv/miv/soc.h
deleted file mode 100644
index d612cdaefa..0000000000
--- a/soc/riscv/microchip_miv/miv/soc.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/*
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef __RISCV32_MIV_SOC_H_
-#define __RISCV32_MIV_SOC_H_
-
-
-#endif /* __RISCV32_MIV_SOC_H_ */
diff --git a/soc/riscv/microchip_miv/polarfire/soc.h b/soc/riscv/microchip_miv/polarfire/soc.h
deleted file mode 100644
index 3bcb9569c6..0000000000
--- a/soc/riscv/microchip_miv/polarfire/soc.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * SPDX-License-Identifier: Apache-2.0
- *
- * Copyright (c) 2020-2021 Microchip Technology Inc
- */
-#ifndef __RISCV64_MPFS_SOC_H_
-#define __RISCV64_MPFS_SOC_H_
-
-#include <zephyr/devicetree.h>
-
-#endif /* __RISCV64_MPFS_SOC_H_ */
diff --git a/soc/riscv/opentitan/soc.h b/soc/riscv/opentitan/soc.h
deleted file mode 100644
index eae12eda48..0000000000
--- a/soc/riscv/opentitan/soc.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * Copyright (c) 2023 Rivos Inc.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef __RISCV_OPENTITAN_SOC_H_
-#define __RISCV_OPENTITAN_SOC_H_
-
-#endif /* __RISCV_OPENTITAN_SOC_H_ */
diff --git a/soc/riscv/renode_virt/soc.h b/soc/riscv/renode_virt/soc.h
deleted file mode 100644
index 3edef49c88..0000000000
--- a/soc/riscv/renode_virt/soc.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * Copyright (c) 2023 Meta
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef __RISCV32_RENODE_SOC_H_
-#define __RISCV32_RENODE_SOC_H_
-
-#endif /* __RISCV32_RENODE_SOC_H_ */
diff --git a/soc/riscv/starfive_jh71xx/jh71xx/soc.h b/soc/riscv/starfive_jh71xx/jh71xx/soc.h
deleted file mode 100644
index df3559c96e..0000000000
--- a/soc/riscv/starfive_jh71xx/jh71xx/soc.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * Copyright (c) 2020 Cobham Gaisler AB
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef __RISCV_VIRT_SOC_H_
-#define __RISCV_VIRT_SOC_H_
-
-#endif
diff --git a/soc/riscv/virt/soc.h b/soc/riscv/virt/soc.h
deleted file mode 100644
index df3559c96e..0000000000
--- a/soc/riscv/virt/soc.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * Copyright (c) 2020 Cobham Gaisler AB
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef __RISCV_VIRT_SOC_H_
-#define __RISCV_VIRT_SOC_H_
-
-#endif