ITE: drivers/gpio: Add gpio_ite_it8xxx2_v2 driver
This driver is made for it82xx2 series. Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit is contained in:
Tim Lin
Anas Nashif
parent
7f3d61c608
commit
491e3e6477
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@ -13,6 +13,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_SIFIVE gpio_sifive.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_GECKO gpio_gecko.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_IMX gpio_imx.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_ITE_IT8XXX2 gpio_ite_it8xxx2.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_ITE_IT8XXX2_V2 gpio_ite_it8xxx2_v2.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_KSCAN_ITE_IT8XXX2 gpio_kscan_ite_it8xxx2.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_MCP23S17 gpio_mcp23s17.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_MCP23XXX gpio_mcp23xxx.c)
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@ -8,6 +8,13 @@ config GPIO_ITE_IT8XXX2
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help
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Enable driver for the ite GPIO controller.
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config GPIO_ITE_IT8XXX2_V2
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bool "ITE IT8XXX2 GPIO driver V2"
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default y
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depends on DT_HAS_ITE_IT8XXX2_GPIO_V2_ENABLED
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help
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Enable driver for the ite GPIO V2 controller.
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config GPIO_KSCAN_ITE_IT8XXX2
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bool "ITE IT8XXX2 GPIO KSCAN driver"
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default y
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456
drivers/gpio/gpio_ite_it8xxx2_v2.c
Normal file
456
drivers/gpio/gpio_ite_it8xxx2_v2.c
Normal file
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@ -0,0 +1,456 @@
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/*
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* Copyright (c) 2023 ITE Corporation. All Rights Reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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*/
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#define DT_DRV_COMPAT ite_it8xxx2_gpio_v2
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#include <errno.h>
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#include <soc.h>
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#include <soc_dt.h>
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#include <string.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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#include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
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#include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
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#include <zephyr/irq.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/types.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(gpio_it8xxx2, LOG_LEVEL_ERR);
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/*
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* Structure gpio_ite_cfg is about the setting of GPIO
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* this config will be used at initial time
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*/
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struct gpio_ite_cfg {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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/* GPIO port data register (bit mapping to pin) */
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uintptr_t reg_gpdr;
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/* GPIO port data mirror register (bit mapping to pin) */
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uintptr_t reg_gpdmr;
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/* GPIO port output type register (bit mapping to pin) */
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uintptr_t reg_gpotr;
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/* GPIO port 1.8V select register (bit mapping to pin) */
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uintptr_t reg_p18scr;
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/* GPIO port control register (byte mapping to pin) */
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uintptr_t reg_gpcr;
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/* Wake up control base register */
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uintptr_t wuc_base[8];
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/* Wake up control mask */
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uint8_t wuc_mask[8];
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/* GPIO's irq */
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uint8_t gpio_irq[8];
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/* Support input voltage selection */
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uint8_t has_volt_sel[8];
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/* Number of pins per group of GPIO */
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uint8_t num_pins;
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};
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/* Structure gpio_ite_data is about callback function */
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struct gpio_ite_data {
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struct gpio_driver_data common;
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sys_slist_t callbacks;
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uint8_t volt_default_set;
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};
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/**
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* Driver functions
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*/
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static int gpio_ite_configure(const struct device *dev,
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gpio_pin_t pin,
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gpio_flags_t flags)
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{
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const struct gpio_ite_cfg *gpio_config = dev->config;
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volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
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volatile uint8_t *reg_gpotr = (uint8_t *)gpio_config->reg_gpotr;
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volatile uint8_t *reg_p18scr = (uint8_t *)gpio_config->reg_p18scr;
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volatile uint8_t *reg_gpcr = (uint8_t *)gpio_config->reg_gpcr + pin;
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struct gpio_ite_data *data = dev->data;
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uint8_t mask = BIT(pin);
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/* Don't support "open source" mode */
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if (((flags & GPIO_SINGLE_ENDED) != 0) &&
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((flags & GPIO_LINE_OPEN_DRAIN) == 0)) {
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return -ENOTSUP;
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}
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if (flags == GPIO_DISCONNECTED) {
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*reg_gpcr = GPCR_PORT_PIN_MODE_TRISTATE;
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/*
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* Since not all GPIOs can be to configured as tri-state,
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* prompt error if pin doesn't support the flag.
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*/
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if (*reg_gpcr != GPCR_PORT_PIN_MODE_TRISTATE) {
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/* Go back to default setting (input) */
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*reg_gpcr = GPCR_PORT_PIN_MODE_INPUT;
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LOG_ERR("Cannot config the node-gpio@%x, pin=%d as tri-state",
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(uint32_t)reg_gpdr, pin);
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return -ENOTSUP;
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}
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/*
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* The following configuration isn't necessary because the pin
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* was configured as disconnected.
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*/
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return 0;
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}
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/*
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* Select open drain first, so that we don't glitch the signal
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* when changing the line to an output.
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*/
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if (flags & GPIO_OPEN_DRAIN) {
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*reg_gpotr |= mask;
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} else {
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*reg_gpotr &= ~mask;
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}
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/* 1.8V or 3.3V */
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if (gpio_config->has_volt_sel[pin]) {
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gpio_flags_t volt = flags & IT8XXX2_GPIO_VOLTAGE_MASK;
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if (volt == IT8XXX2_GPIO_VOLTAGE_1P8) {
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__ASSERT(!(flags & GPIO_PULL_UP),
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"Don't enable internal pullup if 1.8V voltage is used");
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*reg_p18scr |= mask;
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data->volt_default_set &= ~mask;
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} else if (volt == IT8XXX2_GPIO_VOLTAGE_3P3) {
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*reg_p18scr &= ~mask;
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/*
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* A variable is needed to store the difference between
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* 3.3V and default so that the flag can be distinguished
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* between the two in gpio_ite_get_config.
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*/
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data->volt_default_set &= ~mask;
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} else if (volt == IT8XXX2_GPIO_VOLTAGE_DEFAULT) {
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*reg_p18scr &= ~mask;
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data->volt_default_set |= mask;
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} else {
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return -EINVAL;
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}
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}
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/* If output, set level before changing type to an output. */
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if (flags & GPIO_OUTPUT) {
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if (flags & GPIO_OUTPUT_INIT_HIGH) {
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*reg_gpdr |= mask;
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} else if (flags & GPIO_OUTPUT_INIT_LOW) {
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*reg_gpdr &= ~mask;
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}
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}
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/* Set input or output. */
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if (flags & GPIO_OUTPUT) {
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*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_OUTPUT) &
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~GPCR_PORT_PIN_MODE_INPUT;
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} else {
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*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_INPUT) &
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~GPCR_PORT_PIN_MODE_OUTPUT;
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}
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/* Handle pullup / pulldown */
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if (flags & GPIO_PULL_UP) {
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*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_PULLUP) &
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~GPCR_PORT_PIN_MODE_PULLDOWN;
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} else if (flags & GPIO_PULL_DOWN) {
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*reg_gpcr = (*reg_gpcr | GPCR_PORT_PIN_MODE_PULLDOWN) &
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~GPCR_PORT_PIN_MODE_PULLUP;
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} else {
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/* No pull up/down */
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*reg_gpcr &= ~(GPCR_PORT_PIN_MODE_PULLUP |
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GPCR_PORT_PIN_MODE_PULLDOWN);
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}
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return 0;
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}
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#ifdef CONFIG_GPIO_GET_CONFIG
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static int gpio_ite_get_config(const struct device *dev,
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gpio_pin_t pin,
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gpio_flags_t *out_flags)
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{
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const struct gpio_ite_cfg *gpio_config = dev->config;
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volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
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volatile uint8_t *reg_gpotr = (uint8_t *)gpio_config->reg_gpotr;
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volatile uint8_t *reg_p18scr = (uint8_t *)gpio_config->reg_p18scr;
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volatile uint8_t *reg_gpcr = (uint8_t *)gpio_config->reg_gpcr + pin;
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struct gpio_ite_data *data = dev->data;
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uint8_t mask = BIT(pin);
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gpio_flags_t flags = 0;
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/* push-pull or open-drain */
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if (*reg_gpotr & mask) {
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flags |= GPIO_OPEN_DRAIN;
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}
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/* 1.8V or 3.3V */
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if (gpio_config->has_volt_sel[pin]) {
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if (data->volt_default_set & mask) {
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flags |= IT8XXX2_GPIO_VOLTAGE_DEFAULT;
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} else {
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if (*reg_p18scr & mask) {
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flags |= IT8XXX2_GPIO_VOLTAGE_1P8;
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} else {
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flags |= IT8XXX2_GPIO_VOLTAGE_3P3;
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}
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}
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}
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/* set input or output. */
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if (*reg_gpcr & GPCR_PORT_PIN_MODE_OUTPUT) {
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flags |= GPIO_OUTPUT;
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/* set level */
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if (*reg_gpdr & mask) {
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flags |= GPIO_OUTPUT_HIGH;
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} else {
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flags |= GPIO_OUTPUT_LOW;
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}
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}
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if (*reg_gpcr & GPCR_PORT_PIN_MODE_INPUT) {
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flags |= GPIO_INPUT;
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/* pullup / pulldown */
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if (*reg_gpcr & GPCR_PORT_PIN_MODE_PULLUP) {
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flags |= GPIO_PULL_UP;
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}
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if (*reg_gpcr & GPCR_PORT_PIN_MODE_PULLDOWN) {
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flags |= GPIO_PULL_DOWN;
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}
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}
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*out_flags = flags;
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return 0;
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}
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#endif
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static int gpio_ite_port_get_raw(const struct device *dev,
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gpio_port_value_t *value)
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{
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const struct gpio_ite_cfg *gpio_config = dev->config;
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volatile uint8_t *reg_gpdmr = (uint8_t *)gpio_config->reg_gpdmr;
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/* Get raw bits of GPIO mirror register */
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*value = *reg_gpdmr;
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return 0;
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}
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static int gpio_ite_port_set_masked_raw(const struct device *dev,
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gpio_port_pins_t mask,
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gpio_port_value_t value)
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{
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const struct gpio_ite_cfg *gpio_config = dev->config;
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volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
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uint8_t out = *reg_gpdr;
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*reg_gpdr = ((out & ~mask) | (value & mask));
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return 0;
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}
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static int gpio_ite_port_set_bits_raw(const struct device *dev,
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gpio_port_pins_t pins)
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{
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const struct gpio_ite_cfg *gpio_config = dev->config;
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volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
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/* Set raw bits of GPIO data register */
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*reg_gpdr |= pins;
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return 0;
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}
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static int gpio_ite_port_clear_bits_raw(const struct device *dev,
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gpio_port_pins_t pins)
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{
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const struct gpio_ite_cfg *gpio_config = dev->config;
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volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
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/* Clear raw bits of GPIO data register */
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*reg_gpdr &= ~pins;
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return 0;
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}
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static int gpio_ite_port_toggle_bits(const struct device *dev,
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gpio_port_pins_t pins)
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{
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const struct gpio_ite_cfg *gpio_config = dev->config;
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volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;
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/* Toggle raw bits of GPIO data register */
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*reg_gpdr ^= pins;
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return 0;
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}
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static int gpio_ite_manage_callback(const struct device *dev,
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struct gpio_callback *callback,
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bool set)
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{
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struct gpio_ite_data *data = dev->data;
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return gpio_manage_callback(&data->callbacks, callback, set);
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}
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static void gpio_ite_isr(const void *arg)
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{
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const struct device *dev = arg;
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const struct gpio_ite_cfg *gpio_config = dev->config;
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struct gpio_ite_data *data = dev->data;
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uint8_t irq = ite_intc_get_irq_num();
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uint8_t num_pins = gpio_config->num_pins;
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uint8_t pin;
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for (pin = 0; pin <= num_pins; pin++) {
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if (irq == gpio_config->gpio_irq[pin]) {
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volatile uint8_t *reg_base =
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(uint8_t *)gpio_config->wuc_base[pin];
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volatile uint8_t *reg_wuesr = reg_base + 1;
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uint8_t wuc_mask = gpio_config->wuc_mask[pin];
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/* Clear the WUC status register. */
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*reg_wuesr = wuc_mask;
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gpio_fire_callbacks(&data->callbacks, dev, BIT(pin));
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break;
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}
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}
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}
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static int gpio_ite_pin_interrupt_configure(const struct device *dev,
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gpio_pin_t pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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const struct gpio_ite_cfg *gpio_config = dev->config;
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uint8_t gpio_irq = gpio_config->gpio_irq[pin];
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#ifdef CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT
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if (mode == GPIO_INT_MODE_DISABLED || mode == GPIO_INT_MODE_DISABLE_ONLY) {
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#else
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if (mode == GPIO_INT_MODE_DISABLED) {
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#endif /* CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT */
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/* Disable GPIO interrupt */
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irq_disable(gpio_irq);
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return 0;
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#ifdef CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT
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} else if (mode == GPIO_INT_MODE_ENABLE_ONLY) {
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/* Only enable GPIO interrupt */
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irq_enable(gpio_irq);
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return 0;
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#endif /* CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT */
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}
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if (mode == GPIO_INT_MODE_LEVEL) {
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LOG_ERR("Level trigger mode not supported");
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return -ENOTSUP;
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}
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/* Disable irq before configuring it */
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irq_disable(gpio_irq);
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if (trig & GPIO_INT_TRIG_BOTH) {
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volatile uint8_t *reg_base = (uint8_t *)gpio_config->wuc_base[pin];
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volatile uint8_t *reg_wuemr = reg_base;
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volatile uint8_t *reg_wuesr = reg_base + 1;
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volatile uint8_t *reg_wubemr = reg_base + 3;
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uint8_t wuc_mask = gpio_config->wuc_mask[pin];
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/* Set both edges interrupt. */
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if ((trig & GPIO_INT_TRIG_BOTH) == GPIO_INT_TRIG_BOTH) {
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*reg_wubemr |= wuc_mask;
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} else {
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*reg_wubemr &= ~wuc_mask;
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}
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if (trig & GPIO_INT_TRIG_LOW) {
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*reg_wuemr |= wuc_mask;
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} else {
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*reg_wuemr &= ~wuc_mask;
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}
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/*
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* Always write 1 to clear the WUC status register after
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* modifying edge mode selection register (WUBEMR and WUEMR).
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*/
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*reg_wuesr = wuc_mask;
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}
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/* Enable GPIO interrupt */
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irq_connect_dynamic(gpio_irq, 0, gpio_ite_isr, dev, 0);
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irq_enable(gpio_irq);
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return 0;
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}
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static const struct gpio_driver_api gpio_ite_driver_api = {
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.pin_configure = gpio_ite_configure,
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#ifdef CONFIG_GPIO_GET_CONFIG
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.pin_get_config = gpio_ite_get_config,
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#endif
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.port_get_raw = gpio_ite_port_get_raw,
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.port_set_masked_raw = gpio_ite_port_set_masked_raw,
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.port_set_bits_raw = gpio_ite_port_set_bits_raw,
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.port_clear_bits_raw = gpio_ite_port_clear_bits_raw,
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.port_toggle_bits = gpio_ite_port_toggle_bits,
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.pin_interrupt_configure = gpio_ite_pin_interrupt_configure,
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.manage_callback = gpio_ite_manage_callback,
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};
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static int gpio_ite_init(const struct device *dev)
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{
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return 0;
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}
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#define GPIO_ITE_DEV_CFG_DATA(inst) \
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static struct gpio_ite_data gpio_ite_data_##inst; \
|
||||
static const struct gpio_ite_cfg gpio_ite_cfg_##inst = { \
|
||||
.common = { \
|
||||
.port_pin_mask = \
|
||||
GPIO_PORT_PIN_MASK_FROM_DT_INST(inst) \
|
||||
}, \
|
||||
.reg_gpdr = DT_INST_REG_ADDR_BY_IDX(inst, 0), \
|
||||
.reg_gpdmr = DT_INST_REG_ADDR_BY_IDX(inst, 1), \
|
||||
.reg_gpotr = DT_INST_REG_ADDR_BY_IDX(inst, 2), \
|
||||
.reg_p18scr = DT_INST_REG_ADDR_BY_IDX(inst, 3), \
|
||||
.reg_gpcr = DT_INST_REG_ADDR_BY_IDX(inst, 4), \
|
||||
.wuc_base = DT_INST_PROP_OR(inst, wuc_base, {0}), \
|
||||
.wuc_mask = DT_INST_PROP_OR(inst, wuc_mask, {0}), \
|
||||
.gpio_irq = IT8XXX2_DT_GPIO_IRQ_LIST(inst), \
|
||||
.has_volt_sel = DT_INST_PROP_OR(inst, has_volt_sel, {0}), \
|
||||
.num_pins = DT_INST_PROP(inst, ngpios), \
|
||||
}; \
|
||||
DEVICE_DT_INST_DEFINE(inst, \
|
||||
gpio_ite_init, \
|
||||
NULL, \
|
||||
&gpio_ite_data_##inst, \
|
||||
&gpio_ite_cfg_##inst, \
|
||||
PRE_KERNEL_1, \
|
||||
CONFIG_GPIO_INIT_PRIORITY, \
|
||||
&gpio_ite_driver_api);
|
||||
|
||||
DT_INST_FOREACH_STATUS_OKAY(GPIO_ITE_DEV_CFG_DATA)
|
||||
|
||||
static int gpio_it8xxx2_init_set(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN)) {
|
||||
const struct device *const gpiok = DEVICE_DT_GET(DT_NODELABEL(gpiok));
|
||||
const struct device *const gpiol = DEVICE_DT_GET(DT_NODELABEL(gpiol));
|
||||
|
||||
for (int i = 0; i < 8; i++) {
|
||||
gpio_pin_configure(gpiok, i, GPIO_INPUT | GPIO_PULL_DOWN);
|
||||
gpio_pin_configure(gpiol, i, GPIO_INPUT | GPIO_PULL_DOWN);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
SYS_INIT(gpio_it8xxx2_init_set, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY);
|
||||
32
dts/bindings/gpio/ite,it8xxx2-gpio-v2.yaml
Normal file
32
dts/bindings/gpio/ite,it8xxx2-gpio-v2.yaml
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
# Copyright (c) 2023 ITE Corporation. All Rights Reserved.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: This binding gives a base representation of the ITE gpio
|
||||
|
||||
compatible: "ite,it8xxx2-gpio-v2"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
has-volt-sel:
|
||||
type: array
|
||||
description: |
|
||||
Selection of support input voltage 3.3V or 1.8V.
|
||||
|
||||
wuc-base:
|
||||
type: array
|
||||
description: |
|
||||
WUCs are mapped to the pins of GPIO.
|
||||
The WUC groups internal and external inputs, and asserts
|
||||
a wake-up signal to the INTC, allowing the CPU to exit
|
||||
Doze/Deep Doze/Sleep modes.
|
||||
|
||||
wuc-mask:
|
||||
type: array
|
||||
|
||||
gpio-cells:
|
||||
- pin
|
||||
- flags
|
||||
|
|
@ -29,6 +29,407 @@
|
|||
reg = <0x00f03e00 0x2f>;
|
||||
};
|
||||
|
||||
gpioa: gpio@f01601 {
|
||||
compatible = "ite,it8xxx2-gpio-v2";
|
||||
reg = <0x00f01601 1 /* GPDR (set) */
|
||||
0x00f01618 1 /* GPDMR (get) */
|
||||
0x00f01630 1 /* GPOTR */
|
||||
0x00f01648 1 /* P18SCR */
|
||||
0x00f01660 8>; /* GPCR */
|
||||
ngpios = <8>;
|
||||
gpio-controller;
|
||||
interrupts = <IT8XXX2_IRQ_WU91 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU92 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU93 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU80 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU81 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU82 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU83 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU100 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&intc>;
|
||||
wuc-base = <0xf01b20 0xf01b20 0xf01b20 0xf01b1c
|
||||
0xf01b1c 0xf01b1c 0xf01b1c 0xf01b24>;
|
||||
wuc-mask = <BIT(3) BIT(4) BIT(5) BIT(0)
|
||||
BIT(1) BIT(2) BIT(3) BIT(4) >;
|
||||
has-volt-sel = <1 1 1 1 1 1 1 1>;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpiob: gpio@f01602 {
|
||||
compatible = "ite,it8xxx2-gpio-v2";
|
||||
reg = <0x00f01602 1 /* GPDR (set) */
|
||||
0x00f01619 1 /* GPDMR (get) */
|
||||
0x00f01631 1 /* GPOTR */
|
||||
0x00f01649 1 /* P18SCR */
|
||||
0x00f01668 8>; /* GPCR */
|
||||
ngpios = <7>;
|
||||
gpio-controller;
|
||||
interrupts = <IT8XXX2_IRQ_WU101 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU102 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU84 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU103 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU94 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU104 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU105 IRQ_TYPE_LEVEL_HIGH
|
||||
NO_FUNC 0>;
|
||||
interrupt-parent = <&intc>;
|
||||
wuc-base = <0xf01b24 0xf01b24 0xf01b1c 0xf01b24
|
||||
0xf01b20 0xf01b28 0xf01b28 NO_FUNC >;
|
||||
wuc-mask = <BIT(5) BIT(6) BIT(4) BIT(7)
|
||||
BIT(6) BIT(0) BIT(1) 0 >;
|
||||
has-volt-sel = <1 1 1 1 1 1 1 0>;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpioc: gpio@f01603 {
|
||||
compatible = "ite,it8xxx2-gpio-v2";
|
||||
reg = <0x00f01603 1 /* GPDR (set) */
|
||||
0x00f0161a 1 /* GPDMR (get) */
|
||||
0x00f01632 1 /* GPOTR */
|
||||
0x00f0164a 1 /* P18SCR */
|
||||
0x00f01670 8>; /* GPCR */
|
||||
ngpios = <8>;
|
||||
gpio-controller;
|
||||
interrupts = <IT8XXX2_IRQ_WU85 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU107 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU95 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU108 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU22 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU109 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU23 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&intc>;
|
||||
wuc-base = <0xf01b1c 0xf01b28 0xf01b20 0xf01b28
|
||||
0xf01b04 0xf01b28 0xf01b04 0xf01b1c>;
|
||||
wuc-mask = <BIT(5) BIT(3) BIT(7) BIT(4)
|
||||
BIT(2) BIT(5) BIT(3) BIT(6) >;
|
||||
has-volt-sel = <1 1 1 1 1 1 1 1>;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpiod: gpio@f01604 {
|
||||
compatible = "ite,it8xxx2-gpio-v2";
|
||||
reg = <0x00f01604 1 /* GPDR (set) */
|
||||
0x00f0161b 1 /* GPDMR (get) */
|
||||
0x00f01633 1 /* GPOTR */
|
||||
0x00f0164b 1 /* P18SCR */
|
||||
0x00f01678 8>; /* GPCR */
|
||||
ngpios = <8>;
|
||||
gpio-controller;
|
||||
interrupts = <IT8XXX2_IRQ_WU20 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU21 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU24 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU110 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU111 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU112 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU113 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU87 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&intc>;
|
||||
wuc-base = <0xf01b04 0xf01b04 0xf01b04 0xf01b28
|
||||
0xf01b28 0xf01b2c 0xf01b2c 0xf01b1c>;
|
||||
wuc-mask = <BIT(0) BIT(1) BIT(4) BIT(6)
|
||||
BIT(7) BIT(0) BIT(1) BIT(7) >;
|
||||
has-volt-sel = <1 1 1 1 1 1 1 1>;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpioe: gpio@f01605 {
|
||||
compatible = "ite,it8xxx2-gpio-v2";
|
||||
reg = <0x00f01605 1 /* GPDR (set) */
|
||||
0x00f0161c 1 /* GPDMR (get) */
|
||||
0x00f01634 1 /* GPOTR */
|
||||
0x00f0164c 1 /* P18SCR */
|
||||
0x00f01680 8>; /* GPCR */
|
||||
ngpios = <8>;
|
||||
gpio-controller;
|
||||
interrupts = <IT8XXX2_IRQ_WU70 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU71 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU72 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU73 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU114 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU40 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU45 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&intc>;
|
||||
wuc-base = <0xf01b18 0xf01b18 0xf01b18 0xf01b18
|
||||
0xf01b2c 0xf01b0c 0xf01b0c 0xf01b0c>;
|
||||
wuc-mask = <BIT(0) BIT(1) BIT(2) BIT(3)
|
||||
BIT(2) BIT(0) BIT(5) BIT(6) >;
|
||||
has-volt-sel = <1 1 1 1 1 1 1 1>;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpiof: gpio@f01606 {
|
||||
compatible = "ite,it8xxx2-gpio-v2";
|
||||
reg = <0x00f01606 1 /* GPDR (set) */
|
||||
0x00f0161d 1 /* GPDMR (get) */
|
||||
0x00f01635 1 /* GPOTR */
|
||||
0x00f0164d 1 /* P18SCR */
|
||||
0x00f01688 8>; /* GPCR */
|
||||
ngpios = <8>;
|
||||
gpio-controller;
|
||||
interrupts = <IT8XXX2_IRQ_WU96 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU97 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU98 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU99 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU64 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU65 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU66 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&intc>;
|
||||
wuc-base = <0xf01b24 0xf01b24 0xf01b24 0xf01b24
|
||||
0xf01b14 0xf01b14 0xf01b14 0xf01b14>;
|
||||
wuc-mask = <BIT(0) BIT(1) BIT(2) BIT(3)
|
||||
BIT(4) BIT(5) BIT(6) BIT(7) >;
|
||||
has-volt-sel = <1 1 1 1 1 1 1 1>;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpiog: gpio@f01607 {
|
||||
compatible = "ite,it8xxx2-gpio-v2";
|
||||
reg = <0x00f01607 1 /* GPDR (set) */
|
||||
0x00f0161e 1 /* GPDMR (get) */
|
||||
0x00f01636 1 /* GPOTR */
|
||||
0x00f0164e 1 /* P18SCR */
|
||||
0x00f01690 8>; /* GPCR */
|
||||
ngpios = <8>;
|
||||
gpio-controller;
|
||||
interrupts = <IT8XXX2_IRQ_WU115 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU116 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU117 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU123 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU124 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU125 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU118 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU126 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&intc>;
|
||||
wuc-base = <0xf01b2c 0xf01b2c 0xf01b2c 0xf01b30
|
||||
0xf01b30 0xf01b30 0xf01b2c 0xf01b30>;
|
||||
wuc-mask = <BIT(3) BIT(4) BIT(5) BIT(3)
|
||||
BIT(4) BIT(5) BIT(6) BIT(6) >;
|
||||
has-volt-sel = <1 1 1 0 0 0 1 0>;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpioh: gpio@f01608 {
|
||||
compatible = "ite,it8xxx2-gpio-v2";
|
||||
reg = <0x00f01608 1 /* GPDR (set) */
|
||||
0x00f0161f 1 /* GPDMR (get) */
|
||||
0x00f01637 1 /* GPOTR */
|
||||
0x00f0164f 1 /* P18SCR */
|
||||
0x00f01698 8>; /* GPCR */
|
||||
ngpios = <7>;
|
||||
gpio-controller;
|
||||
interrupts = <IT8XXX2_IRQ_WU60 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU61 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU62 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU63 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU88 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU89 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU90 IRQ_TYPE_LEVEL_HIGH
|
||||
NO_FUNC 0>;
|
||||
interrupt-parent = <&intc>;
|
||||
wuc-base = <0xf01b14 0xf01b14 0xf01b14 0xf01b14
|
||||
0xf01b20 0xf01b20 0xf01b20 NO_FUNC >;
|
||||
wuc-mask = <BIT(0) BIT(1) BIT(2) BIT(3)
|
||||
BIT(0) BIT(1) BIT(2) 0 >;
|
||||
has-volt-sel = <1 1 1 1 1 1 1 0>;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpioi: gpio@f01609 {
|
||||
compatible = "ite,it8xxx2-gpio-v2";
|
||||
reg = <0x00f01609 1 /* GPDR (set) */
|
||||
0x00f01620 1 /* GPDMR (get) */
|
||||
0x00f01638 1 /* GPOTR */
|
||||
0x00f01650 1 /* P18SCR */
|
||||
0x00f016a0 8>; /* GPCR */
|
||||
ngpios = <8>;
|
||||
gpio-controller;
|
||||
interrupts = <IT8XXX2_IRQ_WU119 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU120 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU121 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU122 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU74 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU75 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU76 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&intc>;
|
||||
wuc-base = <0xf01b2c 0xf01b30 0xf01b30 0xf01b30
|
||||
0xf01b18 0xf01b18 0xf01b18 0xf01b18>;
|
||||
wuc-mask = <BIT(7) BIT(0) BIT(1) BIT(2)
|
||||
BIT(4) BIT(5) BIT(6) BIT(7) >;
|
||||
has-volt-sel = <1 1 1 1 1 1 1 1>;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpioj: gpio@f0160a {
|
||||
compatible = "ite,it8xxx2-gpio-v2";
|
||||
reg = <0x00f0160a 1 /* GPDR (set) */
|
||||
0x00f01621 1 /* GPDMR (get) */
|
||||
0x00f01639 1 /* GPOTR */
|
||||
0x00f01651 1 /* P18SCR */
|
||||
0x00f016a8 8>; /* GPCR */
|
||||
ngpios = <6>;
|
||||
gpio-controller;
|
||||
interrupts = <IT8XXX2_IRQ_WU128 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU129 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU130 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU131 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU132 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU133 IRQ_TYPE_LEVEL_HIGH
|
||||
NO_FUNC 0
|
||||
NO_FUNC 0>;
|
||||
interrupt-parent = <&intc>;
|
||||
wuc-base = <0xf01b34 0xf01b34 0xf01b34 0xf01b34
|
||||
0xf01b34 0xf01b34 NO_FUNC NO_FUNC >;
|
||||
wuc-mask = <BIT(0) BIT(1) BIT(2) BIT(3)
|
||||
BIT(4) BIT(5) 0 0 >;
|
||||
has-volt-sel = <1 1 1 1 1 1 0 0>;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpiok: gpio@f0160b {
|
||||
compatible = "ite,it8xxx2-gpio-v2";
|
||||
reg = <0x00f0160b 1 /* GPDR (set) */
|
||||
0x00f01622 1 /* GPDMR (get) */
|
||||
0x00f0163a 1 /* GPOTR */
|
||||
0x00f01652 1 /* P18SCR */
|
||||
0x00f016b0 8>; /* GPCR */
|
||||
ngpios = <8>;
|
||||
gpio-controller;
|
||||
interrupts = <IT8XXX2_IRQ_WU50 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU51 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU52 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU53 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU54 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU55 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU56 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&intc>;
|
||||
wuc-base = <0xf01b10 0xf01b10 0xf01b10 0xf01b10
|
||||
0xf01b10 0xf01b10 0xf01b10 0xf01b10>;
|
||||
wuc-mask = <BIT(0) BIT(1) BIT(2) BIT(3)
|
||||
BIT(4) BIT(5) BIT(6) BIT(7) >;
|
||||
has-volt-sel = <1 1 1 1 1 1 1 1>;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpiol: gpio@f0160c {
|
||||
compatible = "ite,it8xxx2-gpio-v2";
|
||||
reg = <0x00f0160c 1 /* GPDR (set) */
|
||||
0x00f01623 1 /* GPDMR (get) */
|
||||
0x00f0163b 1 /* GPOTR */
|
||||
0x00f01653 1 /* P18SCR */
|
||||
0x00f016b8 8>; /* GPCR */
|
||||
ngpios = <8>;
|
||||
gpio-controller;
|
||||
interrupts = <IT8XXX2_IRQ_WU136 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU137 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU138 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU139 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU140 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU141 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU142 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&intc>;
|
||||
wuc-base = <0xf01b38 0xf01b38 0xf01b38 0xf01b38
|
||||
0xf01b38 0xf01b38 0xf01b38 0xf01b38>;
|
||||
wuc-mask = <BIT(0) BIT(1) BIT(2) BIT(3)
|
||||
BIT(4) BIT(5) BIT(6) BIT(7) >;
|
||||
has-volt-sel = <1 1 1 1 1 1 1 1>;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpiom: gpio@f0160d {
|
||||
compatible = "ite,it8xxx2-gpio-v2";
|
||||
reg = <0x00f0160d 1 /* GPDR (set) */
|
||||
0x00f01624 1 /* GPDMR (get) */
|
||||
0x00f0163c 1 /* GPOTR */
|
||||
0x00f01654 1 /* P18SCR */
|
||||
0x00f016c0 8>; /* GPCR */
|
||||
ngpios = <7>;
|
||||
gpio-controller;
|
||||
interrupts = <IT8XXX2_IRQ_WU144 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU145 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU146 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU147 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU148 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU149 IRQ_TYPE_LEVEL_HIGH
|
||||
IT8XXX2_IRQ_WU150 IRQ_TYPE_LEVEL_HIGH
|
||||
NO_FUNC 0>;
|
||||
interrupt-parent = <&intc>;
|
||||
wuc-base = <0xf01b3c 0xf01b3c 0xf01b3c 0xf01b3c
|
||||
0xf01b3c 0xf01b3c 0xf01b3c NO_FUNC >;
|
||||
wuc-mask = <BIT(0) BIT(1) BIT(2) BIT(3)
|
||||
BIT(4) BIT(5) BIT(6) 0 >;
|
||||
has-volt-sel = <1 1 1 1 1 1 1 0>;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpioksi: gpio@f01d08 {
|
||||
compatible = "ite,it8xxx2-gpio-v2";
|
||||
reg = <0x00f01d08 1 /* GPDR (set) */
|
||||
0x00f01d09 1 /* GPDMR (get) */
|
||||
0x00f01d2c 1 /* GPOTR */
|
||||
NO_FUNC 1 /* P18SCR */
|
||||
0x00f01d40 8>; /* GPCR */
|
||||
ngpios = <8>;
|
||||
gpio-controller;
|
||||
interrupts = <NO_FUNC 0
|
||||
NO_FUNC 0
|
||||
NO_FUNC 0
|
||||
NO_FUNC 0
|
||||
NO_FUNC 0
|
||||
NO_FUNC 0
|
||||
NO_FUNC 0
|
||||
NO_FUNC 0>;
|
||||
interrupt-parent = <&intc>;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpioksoh: gpio@f01d01 {
|
||||
compatible = "ite,it8xxx2-gpio-v2";
|
||||
reg = <0x00f01d01 1 /* GPDR (set) */
|
||||
0x00f01d0c 1 /* GPDMR (get) */
|
||||
0x00f01d2d 1 /* GPOTR */
|
||||
NO_FUNC 1 /* P18SCR */
|
||||
0x00f01d50 8>; /* GPCR */
|
||||
ngpios = <8>;
|
||||
gpio-controller;
|
||||
interrupts = <NO_FUNC 0
|
||||
NO_FUNC 0
|
||||
NO_FUNC 0
|
||||
NO_FUNC 0
|
||||
NO_FUNC 0
|
||||
NO_FUNC 0
|
||||
NO_FUNC 0
|
||||
NO_FUNC 0>;
|
||||
interrupt-parent = <&intc>;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpioksol: gpio@f01d00 {
|
||||
compatible = "ite,it8xxx2-gpio-v2";
|
||||
reg = <0x00f01d00 1 /* GPDR (set) */
|
||||
0x00f01d0f 1 /* GPDMR (get) */
|
||||
0x00f01d2e 1 /* GPOTR */
|
||||
NO_FUNC 1 /* P18SCR */
|
||||
0x00f01d48 8>; /* GPCR */
|
||||
ngpios = <8>;
|
||||
gpio-controller;
|
||||
interrupts = <NO_FUNC 0
|
||||
NO_FUNC 0
|
||||
NO_FUNC 0
|
||||
NO_FUNC 0
|
||||
NO_FUNC 0
|
||||
NO_FUNC 0
|
||||
NO_FUNC 0
|
||||
NO_FUNC 0>;
|
||||
interrupt-parent = <&intc>;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
pinctrl: pin-controller {
|
||||
compatible = "ite,it8xxx2-pinctrl";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -310,6 +711,166 @@
|
|||
};
|
||||
};
|
||||
|
||||
wuc1: wakeup-controller@f01b00 {
|
||||
compatible = "ite,it8xxx2-wuc";
|
||||
reg = <0x00f01b00 1 /* WUEMR1 */
|
||||
0x00f01b01 1 /* WUESR1 */
|
||||
0x00f01b02 1 /* WUENR1 */
|
||||
0x00f01b03 1>; /* WUBEMR1 */
|
||||
wakeup-controller;
|
||||
#wuc-cells = <1>;
|
||||
};
|
||||
|
||||
wuc2: wakeup-controller@f01b04 {
|
||||
compatible = "ite,it8xxx2-wuc";
|
||||
reg = <0x00f01b04 1 /* WUEMR2 */
|
||||
0x00f01b05 1 /* WUESR2 */
|
||||
IT8XXX2_WUC_UNUSED_REG 1 /* WUENR2 */
|
||||
0x00f01b07 1>; /* WUBEMR2 */
|
||||
wakeup-controller;
|
||||
#wuc-cells = <1>;
|
||||
};
|
||||
|
||||
wuc3: wakeup-controller@f01b08 {
|
||||
compatible = "ite,it8xxx2-wuc";
|
||||
reg = <0x00f01b08 1 /* WUEMR3 */
|
||||
0x00f01b09 1 /* WUESR3 */
|
||||
0x00f01b0a 1 /* WUENR3 */
|
||||
0x00f01b0b 1>; /* WUBEMR3 */
|
||||
wakeup-controller;
|
||||
#wuc-cells = <1>;
|
||||
};
|
||||
|
||||
wuc4: wakeup-controller@f01b0c {
|
||||
compatible = "ite,it8xxx2-wuc";
|
||||
reg = <0x00f01b0c 1 /* WUEMR4 */
|
||||
0x00f01b0d 1 /* WUESR4 */
|
||||
0x00f01b0e 1 /* WUENR4 */
|
||||
0x00f01b0f 1>; /* WUBEMR4 */
|
||||
wakeup-controller;
|
||||
#wuc-cells = <1>;
|
||||
};
|
||||
|
||||
wuc5: wakeup-controller@f01b10 {
|
||||
compatible = "ite,it8xxx2-wuc";
|
||||
reg = <0x00f01b10 1 /* WUEMR5 */
|
||||
0x00f01b11 1 /* WUESR5 */
|
||||
IT8XXX2_WUC_UNUSED_REG 1 /* WUENR5 */
|
||||
0x00f01b13 1>; /* WUBEMR5 */
|
||||
wakeup-controller;
|
||||
#wuc-cells = <1>;
|
||||
};
|
||||
|
||||
wuc6: wakeup-controller@f01b14 {
|
||||
compatible = "ite,it8xxx2-wuc";
|
||||
reg = <0x00f01b14 1 /* WUEMR6 */
|
||||
0x00f01b15 1 /* WUESR6 */
|
||||
IT8XXX2_WUC_UNUSED_REG 1 /* WUENR6 */
|
||||
0x00f01b17 1>; /* WUBEMR6 */
|
||||
wakeup-controller;
|
||||
#wuc-cells = <1>;
|
||||
};
|
||||
|
||||
wuc7: wakeup-controller@f01b18 {
|
||||
compatible = "ite,it8xxx2-wuc";
|
||||
reg = <0x00f01b18 1 /* WUEMR7 */
|
||||
0x00f01b19 1 /* WUESR7 */
|
||||
IT8XXX2_WUC_UNUSED_REG 1 /* WUENR7 */
|
||||
0x00f01b1b 1>; /* WUBEMR7 */
|
||||
wakeup-controller;
|
||||
#wuc-cells = <1>;
|
||||
};
|
||||
|
||||
wuc8: wakeup-controller@f01b1c {
|
||||
compatible = "ite,it8xxx2-wuc";
|
||||
reg = <0x00f01b1c 1 /* WUEMR8 */
|
||||
0x00f01b1d 1 /* WUESR8 */
|
||||
IT8XXX2_WUC_UNUSED_REG 1 /* WUENR8 */
|
||||
0x00f01b1f 1>; /* WUBEMR8 */
|
||||
wakeup-controller;
|
||||
#wuc-cells = <1>;
|
||||
};
|
||||
|
||||
wuc9: wakeup-controller@f01b20 {
|
||||
compatible = "ite,it8xxx2-wuc";
|
||||
reg = <0x00f01b20 1 /* WUEMR9 */
|
||||
0x00f01b21 1 /* WUESR9 */
|
||||
IT8XXX2_WUC_UNUSED_REG 1 /* WUENR9 */
|
||||
0x00f01b23 1>; /* WUBEMR9 */
|
||||
wakeup-controller;
|
||||
#wuc-cells = <1>;
|
||||
};
|
||||
|
||||
wuc10: wakeup-controller@f01b24 {
|
||||
compatible = "ite,it8xxx2-wuc";
|
||||
reg = <0x00f01b24 1 /* WUEMR10 */
|
||||
0x00f01b25 1 /* WUESR10 */
|
||||
IT8XXX2_WUC_UNUSED_REG 1 /* WUENR10 */
|
||||
0x00f01b27 1>; /* WUBEMR10 */
|
||||
wakeup-controller;
|
||||
#wuc-cells = <1>;
|
||||
};
|
||||
|
||||
wuc11: wakeup-controller@f01b28 {
|
||||
compatible = "ite,it8xxx2-wuc";
|
||||
reg = <0x00f01b28 1 /* WUEMR11 */
|
||||
0x00f01b29 1 /* WUESR11 */
|
||||
IT8XXX2_WUC_UNUSED_REG 1 /* WUENR11 */
|
||||
0x00f01b2b 1>; /* WUBEMR11 */
|
||||
wakeup-controller;
|
||||
#wuc-cells = <1>;
|
||||
};
|
||||
|
||||
wuc12: wakeup-controller@f01b2c {
|
||||
compatible = "ite,it8xxx2-wuc";
|
||||
reg = <0x00f01b2c 1 /* WUEMR12 */
|
||||
0x00f01b2d 1 /* WUESR12 */
|
||||
IT8XXX2_WUC_UNUSED_REG 1 /* WUENR12 */
|
||||
0x00f01b2f 1>; /* WUBEMR12 */
|
||||
wakeup-controller;
|
||||
#wuc-cells = <1>;
|
||||
};
|
||||
|
||||
wuc13: wakeup-controller@f01b30 {
|
||||
compatible = "ite,it8xxx2-wuc";
|
||||
reg = <0x00f01b30 1 /* WUEMR13 */
|
||||
0x00f01b31 1 /* WUESR13 */
|
||||
IT8XXX2_WUC_UNUSED_REG 1 /* WUENR13 */
|
||||
0x00f01b33 1>; /* WUBEMR13 */
|
||||
wakeup-controller;
|
||||
#wuc-cells = <1>;
|
||||
};
|
||||
|
||||
wuc14: wakeup-controller@f01b34 {
|
||||
compatible = "ite,it8xxx2-wuc";
|
||||
reg = <0x00f01b34 1 /* WUEMR14 */
|
||||
0x00f01b35 1 /* WUESR14 */
|
||||
IT8XXX2_WUC_UNUSED_REG 1 /* WUENR14 */
|
||||
0x00f01b37 1>; /* WUBEMR14 */
|
||||
wakeup-controller;
|
||||
#wuc-cells = <1>;
|
||||
};
|
||||
|
||||
wuc15: wakeup-controller@f01b38 {
|
||||
compatible = "ite,it8xxx2-wuc";
|
||||
reg = <0x00f01b38 1 /* WUEMR15 */
|
||||
0x00f01b39 1 /* WUESR15 */
|
||||
IT8XXX2_WUC_UNUSED_REG 1 /* WUENR15 */
|
||||
0x00f01b3b 1>; /* WUBEMR15 */
|
||||
wakeup-controller;
|
||||
#wuc-cells = <1>;
|
||||
};
|
||||
|
||||
wuc16: wakeup-controller@f01b3c {
|
||||
compatible = "ite,it8xxx2-wuc";
|
||||
reg = <0x00f01b3c 1 /* WUEMR16 */
|
||||
0x00f01b3d 1 /* WUESR16 */
|
||||
IT8XXX2_WUC_UNUSED_REG 1 /* WUENR16 */
|
||||
0x00f01b3f 1>; /* WUBEMR16 */
|
||||
wakeup-controller;
|
||||
#wuc-cells = <1>;
|
||||
};
|
||||
|
||||
i2c0: i2c@f04300 {
|
||||
compatible = "ite,enhance-i2c";
|
||||
#address-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -63,4 +63,27 @@
|
|||
inst) \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Macro function to construct it8xxx2 GPIO IRQ in LISTIFY extension.
|
||||
*
|
||||
* @param idx index in LISTIFY extension.
|
||||
* @param inst instance number for compatible defined in DT_DRV_COMPAT.
|
||||
* @return an IRQ number of GPIO.
|
||||
*/
|
||||
#define IT8XXX2_DT_GPIO_IRQ_FUNC(idx, inst) \
|
||||
DT_INST_IRQ_BY_IDX(inst, idx, irq)
|
||||
|
||||
/**
|
||||
* @brief Macro function to construct a list of it8xxx2 GPIO IRQ number
|
||||
* with compatible defined in DT_DRV_COMPAT by LISTIFY func.
|
||||
*
|
||||
* @param inst instance number for compatible defined in DT_DRV_COMPAT.
|
||||
* @return an array of GPIO IRQ number.
|
||||
*/
|
||||
#define IT8XXX2_DT_GPIO_IRQ_LIST(inst) { \
|
||||
LISTIFY(DT_INST_PROP(inst, ngpios), \
|
||||
IT8XXX2_DT_GPIO_IRQ_FUNC, (,), \
|
||||
inst) \
|
||||
}
|
||||
|
||||
#endif /* _ITE_IT8XXX2_SOC_DT_H_ */
|
||||
|
|
|
|||
Loading…
Reference in a new issue