From 4a0b5ce277e5ff8ba9bf1b2d52f79cfd9cf6bc51 Mon Sep 17 00:00:00 2001 From: Felipe Neves Date: Wed, 7 Jul 2021 19:32:00 -0300 Subject: [PATCH] soc: riscv: esp32c3: fix ble controller init By appending the right link layer controller configurarion Signed-off-by: Felipe Neves --- .../riscv/esp32c3_devkitm/Kconfig.defconfig | 3 --- .../esp32c3_devkitm/esp32c3_devkitm_defconfig | 3 --- soc/riscv/esp32c3/Kconfig.soc | 1 + soc/riscv/esp32c3/linker.ld | 20 ------------------- soc/riscv/esp32c3/soc.c | 6 ++++++ west.yml | 2 +- 6 files changed, 8 insertions(+), 27 deletions(-) diff --git a/boards/riscv/esp32c3_devkitm/Kconfig.defconfig b/boards/riscv/esp32c3_devkitm/Kconfig.defconfig index fd15bd80fa..3276547dba 100644 --- a/boards/riscv/esp32c3_devkitm/Kconfig.defconfig +++ b/boards/riscv/esp32c3_devkitm/Kconfig.defconfig @@ -12,9 +12,6 @@ if BT config HEAP_MEM_POOL_SIZE default 16384 -config ENTROPY_GENERATOR - default y - choice BT_HCI_BUS_TYPE default BT_ESP32 endchoice diff --git a/boards/riscv/esp32c3_devkitm/esp32c3_devkitm_defconfig b/boards/riscv/esp32c3_devkitm/esp32c3_devkitm_defconfig index 8313cb0e8d..f2361455ae 100644 --- a/boards/riscv/esp32c3_devkitm/esp32c3_devkitm_defconfig +++ b/boards/riscv/esp32c3_devkitm/esp32c3_devkitm_defconfig @@ -10,6 +10,3 @@ CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y CONFIG_UART_ROM_ESP32C3=y CONFIG_XIP=n -CONFIG_HEAP_MEM_POOL_SIZE=16384 -CONFIG_BT=y - diff --git a/soc/riscv/esp32c3/Kconfig.soc b/soc/riscv/esp32c3/Kconfig.soc index b727509d33..5ae33a9c19 100644 --- a/soc/riscv/esp32c3/Kconfig.soc +++ b/soc/riscv/esp32c3/Kconfig.soc @@ -5,6 +5,7 @@ config SOC_ESP32C3 bool "ESP32C3" select RISCV select RISCV_SOC_INIT_GP_VALUE + select DYNAMIC_INTERRUPTS config IDF_TARGET_ESP32C3 bool "ESP32C3 as target board" diff --git a/soc/riscv/esp32c3/linker.ld b/soc/riscv/esp32c3/linker.ld index 4ac7860ab8..b9dbce3041 100644 --- a/soc/riscv/esp32c3/linker.ld +++ b/soc/riscv/esp32c3/linker.ld @@ -150,15 +150,6 @@ SECTIONS .dram0.data : { _data_start = ABSOLUTE(.); - _bt_data_start = ABSOLUTE(.); - *libbt.a:(.data .data.*) - . = ALIGN (4); - _bt_data_end = ABSOLUTE(.); - _btdm_data_start = ABSOLUTE(.); - *libbtdm_app.a:(.data .data.*) - . = ALIGN (4); - _btdm_data_end = ABSOLUTE(.); - *(.data) *(.data.*) *(.gnu.linkonce.d.*) @@ -197,16 +188,6 @@ SECTIONS { . = ALIGN (8); __bss_start = ABSOLUTE(.); - - _bt_bss_start = ABSOLUTE(.); - *libbt.a:(.bss .bss.* COMMON) - . = ALIGN (4); - _bt_bss_end = ABSOLUTE(.); - _btdm_bss_start = ABSOLUTE(.); - *libbtdm_app.a:(.bss .bss.* COMMON) - . = ALIGN (4); - _btdm_bss_end = ABSOLUTE(.); - *(.dynsbss) *(.sbss) *(.sbss.*) @@ -231,7 +212,6 @@ SECTIONS *(.noinit) *(".noinit.*") . = ALIGN (8); - _heap_start = ABSOLUTE(.); } GROUP_LINK_IN(RAMABLE_REGION) .flash.text : ALIGN(4) diff --git a/soc/riscv/esp32c3/soc.c b/soc/riscv/esp32c3/soc.c index 0b35b297dd..2ebb6ca250 100644 --- a/soc/riscv/esp32c3/soc.c +++ b/soc/riscv/esp32c3/soc.c @@ -94,6 +94,12 @@ void __attribute__((section(".iram1"))) __start(void) /* set global esp32c3's INTC masking level */ esprv_intc_int_set_threshold(1); + /* Enable wireless phy subsystem clock, + * This needs to be done before the kernel starts + */ + REG_CLR_BIT(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_SDIOSLAVE_EN); + SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN); + /* Start Zephyr */ _PrepC(); diff --git a/west.yml b/west.yml index 49054d47ba..a1a6567dc4 100644 --- a/west.yml +++ b/west.yml @@ -62,7 +62,7 @@ manifest: groups: - hal - name: hal_espressif - revision: 7b19e8c4a66fa6fb05c5862175edb12e15659b72 + revision: 56a84e45eeaf3b6dea88b198c5c252c06f8ac774 path: modules/hal/espressif groups: - hal