patrick/zephyr
1
0
Fork 0
Code Issues Pull requests Actions 7 Packages Projects Releases Wiki Activity

dts: x86: RAM start address needs to be page aligned for arduino 101.

Browse source 
When CONFIG_X86_MMU is enabled for arduino 101 the start address
should be aligned to 4kB. If not aligned the page tables would not
be created and the build fails.

Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
This commit is contained in:
Adithya Baglody 2017-11-08 16:00:17 +05:30 committed by Andrew Boie
parent 8d0a80c6a9
commit 4a20aad15a
4 changed files with 5 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
arch/arc/soc/quark_se_c1000_ss/Kconfig.defconfig
View file

@ -40,7 +40,7 @@ config SRAM_BASE_ADDRESS
config SRAM_SIZE
default 16 if NSIM
default 24
default 27
config ICCM_BASE_ADDRESS
default 0xFFFFFFFF

2
arch/x86/soc/intel_quark/quark_se/Kconfig.defconfig.series
View file

@ -27,7 +27,7 @@ config PHYS_LOAD_ADDR
endif
config RAM_SIZE
default 55
default 52
config ROM_SIZE
default 144

5
dts/x86/intel_curie.dtsi
View file

@ -27,13 +27,12 @@
reg = <0x40030000 DT_FLASH_SIZE>;
};
sram0: memory@a8006400 {
sram0: memory@a8007000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0xa8006400 DT_SRAM_SIZE>;
reg = <0xa8007000 DT_SRAM_SIZE>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;

2
dts/x86/mem.h
View file

@ -5,7 +5,7 @@
#if defined(CONFIG_SOC_QUARK_SE_C1000)
#define DT_FLASH_SIZE __SIZE_K(144)
#define DT_SRAM_SIZE __SIZE_K(55)
#define DT_SRAM_SIZE __SIZE_K(52)
#elif defined(CONFIG_SOC_QUARK_D2000)
#define DT_FLASH_SIZE __SIZE_K(32)
#define DT_SRAM_SIZE __SIZE_K(8)