drivers: clock_control: gd32: initial support
This patch adds a clock control driver for GD32 platforms. It is important to note that the driver is only able to handle peripheral clocks, but not "system clocks" (e.g. PLL settings, SYS_CK, etc.). On some similar platforms (STM32) this task is embedded in the same clock driver, performed at init time but with no options to do any manipulation at runtime via the API calls. The clock control API as-is is really orthogonal to "system clocks", and it is arguably a bad idea to embed system clock init code in a clock control driver. It can be done at SoC level still using Devicetree as a source of hardware description/initial configuration. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit is contained in:
Gerard Marull-Paretas
Carles Cufí
parent
424f696ce9
commit
4aa31b4526
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@ -5,6 +5,7 @@ zephyr_library()
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_BEETLE beetle_clock_control.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_CAVS clock_control_cavs.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_ESP32 clock_control_esp32.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_GD32 clock_control_gd32.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_LITEX clock_control_litex.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_LPC11U6X clock_control_lpc11u6x.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCHP_XEC clock_control_mchp_xec.c)
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@ -64,4 +64,6 @@ source "drivers/clock_control/Kconfig.cavs"
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source "drivers/clock_control/Kconfig.aspeed"
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source "drivers/clock_control/Kconfig.gd32"
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endif # CLOCK_CONTROL
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9
drivers/clock_control/Kconfig.gd32
Normal file
9
drivers/clock_control/Kconfig.gd32
Normal file
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@ -0,0 +1,9 @@
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# Copyright (c) 2022 Teslabs Engineering S.L.
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# SPDX-License-Identifier: Apache-2.0
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config CLOCK_CONTROL_GD32
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bool "GD32 clock control"
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default y
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depends on DT_HAS_GD_GD32_CCTL_ENABLED
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help
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Enable driver for Gigadevice Reset Clock Unit (RCU).
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139
drivers/clock_control/clock_control_gd32.c
Normal file
139
drivers/clock_control/clock_control_gd32.c
Normal file
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@ -0,0 +1,139 @@
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/*
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* Copyright (c) 2022 Teslabs Engineering S.L.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT gd_gd32_cctl
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#include <stdint.h>
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#include <zephyr/device.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/gd32.h>
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#include <gd32_regs.h>
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/** RCU offset (from id cell) */
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#define GD32_CLOCK_ID_OFFSET(id) (((id) >> 6U) & 0xFFU)
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/** RCU configuration bit (from id cell) */
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#define GD32_CLOCK_ID_BIT(id) ((id)&0x1FU)
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/** AHB prescaler exponents */
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static const uint8_t ahb_exp[16] = {
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0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U,
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};
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/** APB1 prescaler exponents */
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static const uint8_t apb1_exp[8] = {
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0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U,
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};
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/** APB2 prescaler exponents */
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static const uint8_t apb2_exp[8] = {
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0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U,
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};
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struct clock_control_gd32_config {
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uint32_t base;
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};
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static int clock_control_gd32_on(const struct device *dev,
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clock_control_subsys_t sys)
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{
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const struct clock_control_gd32_config *config = dev->config;
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uint16_t id = *(uint16_t *)sys;
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sys_set_bit(config->base + GD32_CLOCK_ID_OFFSET(id),
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GD32_CLOCK_ID_BIT(id));
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return 0;
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}
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static int clock_control_gd32_off(const struct device *dev,
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clock_control_subsys_t sys)
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{
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const struct clock_control_gd32_config *config = dev->config;
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uint16_t id = *(uint16_t *)sys;
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sys_clear_bit(config->base + GD32_CLOCK_ID_OFFSET(id),
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GD32_CLOCK_ID_BIT(id));
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return 0;
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}
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static int clock_control_gd32_get_rate(const struct device *dev,
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clock_control_subsys_t sys,
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uint32_t *rate)
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{
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const struct clock_control_gd32_config *config = dev->config;
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uint16_t id = *(uint16_t *)sys;
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uint32_t cfg;
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uint8_t psc;
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cfg = sys_read32(config->base + RCU_CFG0_OFFSET);
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switch (GD32_CLOCK_ID_OFFSET(id)) {
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#if defined(CONFIG_SOC_SERIES_GD32F4XX)
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case RCU_AHB1EN_OFFSET:
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case RCU_AHB2EN_OFFSET:
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case RCU_AHB3EN_OFFSET:
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#else
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case RCU_AHBEN_OFFSET:
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#endif
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psc = (cfg & RCU_CFG0_AHBPSC_MSK) >> RCU_CFG0_AHBPSC_POS;
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*rate = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC >> ahb_exp[psc];
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break;
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case RCU_APB1EN_OFFSET:
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#if !defined(CONFIG_SOC_SERIES_GD32VF103)
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case RCU_ADDAPB1EN_OFFSET:
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#endif
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psc = (cfg & RCU_CFG0_APB1PSC_MSK) >> RCU_CFG0_APB1PSC_POS;
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*rate = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC >> apb1_exp[psc];
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break;
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case RCU_APB2EN_OFFSET:
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psc = (cfg & RCU_CFG0_APB2PSC_MSK) >> RCU_CFG0_APB2PSC_POS;
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*rate = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC >> apb2_exp[psc];
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static enum clock_control_status
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clock_control_gd32_get_status(const struct device *dev,
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clock_control_subsys_t sys)
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{
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const struct clock_control_gd32_config *config = dev->config;
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uint16_t id = *(uint16_t *)sys;
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if (sys_test_bit(config->base + GD32_CLOCK_ID_OFFSET(id),
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GD32_CLOCK_ID_BIT(id)) != 0) {
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return CLOCK_CONTROL_STATUS_ON;
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}
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return CLOCK_CONTROL_STATUS_OFF;
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}
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static struct clock_control_driver_api clock_control_gd32_api = {
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.on = clock_control_gd32_on,
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.off = clock_control_gd32_off,
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.get_rate = clock_control_gd32_get_rate,
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.get_status = clock_control_gd32_get_status,
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};
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static int clock_control_gd32_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return 0;
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}
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static const struct clock_control_gd32_config config = {
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.base = DT_REG_ADDR(DT_INST_PARENT(0)),
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};
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DEVICE_DT_INST_DEFINE(0, clock_control_gd32_init, NULL, NULL, &config,
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PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
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&clock_control_gd32_api);
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@ -9,6 +9,7 @@
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/pwm/pwm.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/clock/gd32e10x-clocks.h>
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#include <zephyr/dt-bindings/reset/gd32e10x.h>
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/ {
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@ -35,6 +36,12 @@
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reg = <0x40021000 0x400>;
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status = "okay";
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cctl: clock-controller {
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compatible = "gd,gd32-cctl";
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#clock-cells = <1>;
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status = "okay";
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};
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rctl: reset-controller {
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compatible = "gd,gd32-rctl";
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#reset-cells = <1>;
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@ -9,6 +9,7 @@
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/pwm/pwm.h>
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#include <zephyr/dt-bindings/clock/gd32e50x-clocks.h>
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#include <zephyr/dt-bindings/reset/gd32e50x.h>
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/ {
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@ -35,6 +36,12 @@
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reg = <0x40021000 0x400>;
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status = "okay";
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cctl: clock-controller {
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compatible = "gd,gd32-cctl";
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#clock-cells = <1>;
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status = "okay";
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};
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rctl: reset-controller {
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compatible = "gd,gd32-rctl";
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#reset-cells = <1>;
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@ -8,6 +8,7 @@
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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/adc/gd32f3x0.h>
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#include <zephyr/dt-bindings/clock/gd32f3x0-clocks.h>
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#include <zephyr/dt-bindings/reset/gd32f3x0.h>
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/ {
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@ -32,6 +33,12 @@
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reg = <0x40021000 0x400>;
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status = "okay";
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cctl: clock-controller {
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compatible = "gd,gd32-cctl";
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#clock-cells = <1>;
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status = "okay";
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};
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rctl: reset-controller {
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compatible = "gd,gd32-rctl";
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#reset-cells = <1>;
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@ -9,6 +9,7 @@
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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/pwm/pwm.h>
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#include <zephyr/dt-bindings/clock/gd32f403-clocks.h>
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#include <zephyr/dt-bindings/reset/gd32f403.h>
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/ {
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@ -41,6 +42,12 @@
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reg = <0x40021000 0x400>;
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status = "okay";
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cctl: clock-controller {
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compatible = "gd,gd32-cctl";
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#clock-cells = <1>;
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status = "okay";
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};
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rctl: reset-controller {
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compatible = "gd,gd32-rctl";
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#reset-cells = <1>;
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@ -8,6 +8,7 @@
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/pwm/pwm.h>
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#include <zephyr/dt-bindings/clock/gd32f4xx-clocks.h>
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#include <zephyr/dt-bindings/reset/gd32f4xx.h>
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/ {
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@ -40,6 +41,12 @@
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reg = <0x40023800 0x400>;
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status = "okay";
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cctl: clock-controller {
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compatible = "gd,gd32-cctl";
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#clock-cells = <1>;
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status = "okay";
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};
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rctl: reset-controller {
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compatible = "gd,gd32-rctl";
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#reset-cells = <1>;
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32
dts/bindings/clock/gd,gd32-cctl.yaml
Normal file
32
dts/bindings/clock/gd,gd32-cctl.yaml
Normal file
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@ -0,0 +1,32 @@
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# Copyright (c) 2022, Teslabs Engineering S.L.
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# SPDX-License-Identifier: Apache-2.0
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description: |
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Gigadevice Reset and Clock Unit (RCU) if a multi-function peripheral in
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charge of reset control (RCTL) and clock control (CCTL) for all SoC
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peripherals. This binding represents the clock controller (CCTL).
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To specify the clocks in a peripheral, the standard clocks property needs
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to be used, e.g.:
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gpioa: gpio@xxx {
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...
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/* cell encodes RCU register offset and control bit position */
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clocks = <&cctl GD32_CLOCK_GPIOA>;
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...
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}
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Predefined RCU clock cells are available in
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include/zephyr/dts-bindings/clock/gd32{xxx}-clocks.h header files, where {xxx}
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corresponds to the SoC series, e.g. f4xx.
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compatible: "gd,gd32-cctl"
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include: [clock-controller.yaml, base.yaml]
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properties:
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"#clock-cells":
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const: 1
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clock-cells:
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- id
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@ -9,6 +9,7 @@
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#include <zephyr/dt-bindings/timer/nuclei-systimer.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/pwm/pwm.h>
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#include <zephyr/dt-bindings/clock/gd32vf103-clocks.h>
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#include <zephyr/dt-bindings/reset/gd32vf103.h>
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/ {
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@ -61,6 +62,12 @@
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reg = <0x40021000 0x400>;
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status = "okay";
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cctl: clock-controller {
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compatible = "gd,gd32-cctl";
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#clock-cells = <1>;
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status = "okay";
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};
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rctl: reset-controller {
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compatible = "gd,gd32-rctl";
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#reset-cells = <1>;
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21
include/zephyr/drivers/clock_control/gd32.h
Normal file
21
include/zephyr/drivers/clock_control/gd32.h
Normal file
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@ -0,0 +1,21 @@
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/*
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* Copyright (c) 2022 Teslabs Engineering S.L.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_GD32_H_
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#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_GD32_H_
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#include <zephyr/device.h>
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/**
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* @brief Obtain a reference to the GD32 clock controller.
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*
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* There is a single clock controller in the GD32: cctl. The device can be
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* used without checking for it to be ready since it has no initialization
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* code subject to failures.
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*/
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#define GD32_CLOCK_CONTROLLER DEVICE_DT_GET(DT_NODELABEL(cctl))
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#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_GD32_H_ */
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23
include/zephyr/dt-bindings/clock/gd32-clocks-common.h
Normal file
23
include/zephyr/dt-bindings/clock/gd32-clocks-common.h
Normal file
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@ -0,0 +1,23 @@
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/*
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* Copyright (c) 2022 Teslabs Engineering S.L.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32_COMMON_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32_COMMON_H_
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/**
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* Encode RCU register offset and configuration bit.
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*
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* - 0..5: bit number
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* - 6..14: offset
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* - 15: reserved
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*
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* @param reg RCU register name (expands to GD32_{reg}_OFFSET)
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* @param bit Configuration bit
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*/
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#define GD32_CLOCK_CONFIG(reg, bit) \
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(((GD32_ ## reg ## _OFFSET) << 6U) | (bit))
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32_H_ */
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83
include/zephyr/dt-bindings/clock/gd32e10x-clocks.h
Normal file
83
include/zephyr/dt-bindings/clock/gd32e10x-clocks.h
Normal file
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@ -0,0 +1,83 @@
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/*
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* Copyright (c) 2022 Teslabs Engineering S.L.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32E10X_CLOCKS_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32E10X_CLOCKS_H_
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#include "gd32-clocks-common.h"
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/**
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* @name Register offsets
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* @{
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*/
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#define GD32_AHBEN_OFFSET 0x14U
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#define GD32_APB1EN_OFFSET 0x1CU
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#define GD32_APB2EN_OFFSET 0x18U
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#define GD32_ADDAPB1EN_OFFSET 0xE4U
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/** @} */
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/**
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* @name Clock enable/disable definitions for peripherals
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* @{
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*/
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/* AHB peripherals */
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#define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHBEN, 0U)
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#define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHBEN, 1U)
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#define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U)
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#define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U)
|
||||
#define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U)
|
||||
#define GD32_CLOCK_EXMC GD32_CLOCK_CONFIG(AHBEN, 8U)
|
||||
#define GD32_CLOCK_USBFS GD32_CLOCK_CONFIG(AHBEN, 12U)
|
||||
|
||||
/* APB1 peripherals */
|
||||
#define GD32_CLOCK_TIMER1 GD32_CLOCK_CONFIG(APB1EN, 0U)
|
||||
#define GD32_CLOCK_TIMER2 GD32_CLOCK_CONFIG(APB1EN, 1U)
|
||||
#define GD32_CLOCK_TIMER3 GD32_CLOCK_CONFIG(APB1EN, 2U)
|
||||
#define GD32_CLOCK_TIMER4 GD32_CLOCK_CONFIG(APB1EN, 3U)
|
||||
#define GD32_CLOCK_TIMER5 GD32_CLOCK_CONFIG(APB1EN, 4U)
|
||||
#define GD32_CLOCK_TIMER6 GD32_CLOCK_CONFIG(APB1EN, 5U)
|
||||
#define GD32_CLOCK_TIMER11 GD32_CLOCK_CONFIG(APB1EN, 6U)
|
||||
#define GD32_CLOCK_TIMER12 GD32_CLOCK_CONFIG(APB1EN, 7U)
|
||||
#define GD32_CLOCK_TIMER13 GD32_CLOCK_CONFIG(APB1EN, 8U)
|
||||
#define GD32_CLOCK_WWDGT GD32_CLOCK_CONFIG(APB1EN, 11U)
|
||||
#define GD32_CLOCK_SPI1 GD32_CLOCK_CONFIG(APB1EN, 14U)
|
||||
#define GD32_CLOCK_SPI2 GD32_CLOCK_CONFIG(APB1EN, 15U)
|
||||
#define GD32_CLOCK_USART1 GD32_CLOCK_CONFIG(APB1EN, 17U)
|
||||
#define GD32_CLOCK_USART2 GD32_CLOCK_CONFIG(APB1EN, 18U)
|
||||
#define GD32_CLOCK_UART3 GD32_CLOCK_CONFIG(APB1EN, 19U)
|
||||
#define GD32_CLOCK_UART4 GD32_CLOCK_CONFIG(APB1EN, 20U)
|
||||
#define GD32_CLOCK_I2C0 GD32_CLOCK_CONFIG(APB1EN, 21U)
|
||||
#define GD32_CLOCK_I2C1 GD32_CLOCK_CONFIG(APB1EN, 22U)
|
||||
#define GD32_CLOCK_BKPI GD32_CLOCK_CONFIG(APB1EN, 27U)
|
||||
#define GD32_CLOCK_PMU GD32_CLOCK_CONFIG(APB1EN, 28U)
|
||||
#define GD32_CLOCK_DAC GD32_CLOCK_CONFIG(APB1EN, 29U)
|
||||
|
||||
/* APB2 peripherals */
|
||||
#define GD32_CLOCK_AFIO GD32_CLOCK_CONFIG(APB2EN, 0U)
|
||||
#define GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(APB2EN, 2U)
|
||||
#define GD32_CLOCK_GPIOB GD32_CLOCK_CONFIG(APB2EN, 3U)
|
||||
#define GD32_CLOCK_GPIOC GD32_CLOCK_CONFIG(APB2EN, 4U)
|
||||
#define GD32_CLOCK_GPIOD GD32_CLOCK_CONFIG(APB2EN, 5U)
|
||||
#define GD32_CLOCK_GPIOE GD32_CLOCK_CONFIG(APB2EN, 6U)
|
||||
#define GD32_CLOCK_ADC0 GD32_CLOCK_CONFIG(APB2EN, 9U)
|
||||
#define GD32_CLOCK_ADC1 GD32_CLOCK_CONFIG(APB2EN, 10U)
|
||||
#define GD32_CLOCK_TIMER0 GD32_CLOCK_CONFIG(APB2EN, 11U)
|
||||
#define GD32_CLOCK_SPI0 GD32_CLOCK_CONFIG(APB2EN, 12U)
|
||||
#define GD32_CLOCK_TIMER7 GD32_CLOCK_CONFIG(APB2EN, 13U)
|
||||
#define GD32_CLOCK_USART0 GD32_CLOCK_CONFIG(APB2EN, 14U)
|
||||
#define GD32_CLOCK_TIMER8 GD32_CLOCK_CONFIG(APB2EN, 19U)
|
||||
#define GD32_CLOCK_TIMER9 GD32_CLOCK_CONFIG(APB2EN, 20U)
|
||||
#define GD32_CLOCK_TIMER10 GD32_CLOCK_CONFIG(APB2EN, 21U)
|
||||
|
||||
/* APB1 additional peripherals */
|
||||
#define GD32_CLOCK_CTC GD32_CLOCK_CONFIG(ADDAPB1EN, 27U)
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32E10X_CLOCKS_H_ */
|
||||
99
include/zephyr/dt-bindings/clock/gd32e50x-clocks.h
Normal file
99
include/zephyr/dt-bindings/clock/gd32e50x-clocks.h
Normal file
|
|
@ -0,0 +1,99 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Teslabs Engineering S.L.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32E50X_CLOCKS_H_
|
||||
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32E50X_CLOCKS_H_
|
||||
|
||||
#include "gd32-clocks-common.h"
|
||||
|
||||
/**
|
||||
* @name Register offsets
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GD32_AHBEN_OFFSET 0x14U
|
||||
#define GD32_APB1EN_OFFSET 0x1CU
|
||||
#define GD32_APB2EN_OFFSET 0x18U
|
||||
#define GD32_ADDAPB1EN_OFFSET 0xE4U
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Clock enable/disable definitions for peripherals
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* AHB peripherals */
|
||||
#define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHBEN, 0U)
|
||||
#define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHBEN, 1U)
|
||||
#define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U)
|
||||
#define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U)
|
||||
#define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U)
|
||||
#define GD32_CLOCK_EXMC GD32_CLOCK_CONFIG(AHBEN, 8U)
|
||||
#define GD32_CLOCK_USBHS GD32_CLOCK_CONFIG(AHBEN, 12U)
|
||||
#define GD32_CLOCK_ULPI GD32_CLOCK_CONFIG(AHBEN, 13U)
|
||||
#define GD32_CLOCK_ENET GD32_CLOCK_CONFIG(AHBEN, 14U)
|
||||
#define GD32_CLOCK_ENETTX GD32_CLOCK_CONFIG(AHBEN, 15U)
|
||||
#define GD32_CLOCK_ENETRX GD32_CLOCK_CONFIG(AHBEN, 16U)
|
||||
#define GD32_CLOCK_TMU GD32_CLOCK_CONFIG(AHBEN, 30U)
|
||||
#define GD32_CLOCK_SQPI GD32_CLOCK_CONFIG(AHBEN, 31U)
|
||||
|
||||
/* APB1 peripherals */
|
||||
#define GD32_CLOCK_TIMER1 GD32_CLOCK_CONFIG(APB1EN, 0U)
|
||||
#define GD32_CLOCK_TIMER2 GD32_CLOCK_CONFIG(APB1EN, 1U)
|
||||
#define GD32_CLOCK_TIMER3 GD32_CLOCK_CONFIG(APB1EN, 2U)
|
||||
#define GD32_CLOCK_TIMER4 GD32_CLOCK_CONFIG(APB1EN, 3U)
|
||||
#define GD32_CLOCK_TIMER5 GD32_CLOCK_CONFIG(APB1EN, 4U)
|
||||
#define GD32_CLOCK_TIMER6 GD32_CLOCK_CONFIG(APB1EN, 5U)
|
||||
#define GD32_CLOCK_TIMER11 GD32_CLOCK_CONFIG(APB1EN, 6U)
|
||||
#define GD32_CLOCK_TIMER12 GD32_CLOCK_CONFIG(APB1EN, 7U)
|
||||
#define GD32_CLOCK_TIMER13 GD32_CLOCK_CONFIG(APB1EN, 8U)
|
||||
#define GD32_CLOCK_WWDGT GD32_CLOCK_CONFIG(APB1EN, 11U)
|
||||
#define GD32_CLOCK_SPI1 GD32_CLOCK_CONFIG(APB1EN, 14U)
|
||||
#define GD32_CLOCK_SPI2 GD32_CLOCK_CONFIG(APB1EN, 15U)
|
||||
#define GD32_CLOCK_USART1 GD32_CLOCK_CONFIG(APB1EN, 17U)
|
||||
#define GD32_CLOCK_USART2 GD32_CLOCK_CONFIG(APB1EN, 18U)
|
||||
#define GD32_CLOCK_UART3 GD32_CLOCK_CONFIG(APB1EN, 19U)
|
||||
#define GD32_CLOCK_UART4 GD32_CLOCK_CONFIG(APB1EN, 20U)
|
||||
#define GD32_CLOCK_I2C0 GD32_CLOCK_CONFIG(APB1EN, 21U)
|
||||
#define GD32_CLOCK_I2C1 GD32_CLOCK_CONFIG(APB1EN, 22U)
|
||||
#define GD32_CLOCK_I2C2 GD32_CLOCK_CONFIG(APB1EN, 24U)
|
||||
#define GD32_CLOCK_CAN0 GD32_CLOCK_CONFIG(APB1EN, 25U)
|
||||
#define GD32_CLOCK_CAN1 GD32_CLOCK_CONFIG(APB1EN, 26U)
|
||||
#define GD32_CLOCK_BKPI GD32_CLOCK_CONFIG(APB1EN, 27U)
|
||||
#define GD32_CLOCK_PMU GD32_CLOCK_CONFIG(APB1EN, 28U)
|
||||
#define GD32_CLOCK_DAC GD32_CLOCK_CONFIG(APB1EN, 29U)
|
||||
|
||||
/* APB2 peripherals */
|
||||
#define GD32_CLOCK_AFIO GD32_CLOCK_CONFIG(APB2EN, 0U)
|
||||
#define GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(APB2EN, 2U)
|
||||
#define GD32_CLOCK_GPIOB GD32_CLOCK_CONFIG(APB2EN, 3U)
|
||||
#define GD32_CLOCK_GPIOC GD32_CLOCK_CONFIG(APB2EN, 4U)
|
||||
#define GD32_CLOCK_GPIOD GD32_CLOCK_CONFIG(APB2EN, 5U)
|
||||
#define GD32_CLOCK_GPIOE GD32_CLOCK_CONFIG(APB2EN, 6U)
|
||||
#define GD32_CLOCK_GPIOF GD32_CLOCK_CONFIG(APB2EN, 7U)
|
||||
#define GD32_CLOCK_GPIOG GD32_CLOCK_CONFIG(APB2EN, 8U)
|
||||
#define GD32_CLOCK_ADC0 GD32_CLOCK_CONFIG(APB2EN, 9U)
|
||||
#define GD32_CLOCK_ADC1 GD32_CLOCK_CONFIG(APB2EN, 10U)
|
||||
#define GD32_CLOCK_TIMER0 GD32_CLOCK_CONFIG(APB2EN, 11U)
|
||||
#define GD32_CLOCK_SPI0 GD32_CLOCK_CONFIG(APB2EN, 12U)
|
||||
#define GD32_CLOCK_TIMER7 GD32_CLOCK_CONFIG(APB2EN, 13U)
|
||||
#define GD32_CLOCK_USART0 GD32_CLOCK_CONFIG(APB2EN, 14U)
|
||||
#define GD32_CLOCK_ADC2 GD32_CLOCK_CONFIG(APB2EN, 15U)
|
||||
#define GD32_CLOCK_TIMER8 GD32_CLOCK_CONFIG(APB2EN, 19U)
|
||||
#define GD32_CLOCK_TIMER9 GD32_CLOCK_CONFIG(APB2EN, 20U)
|
||||
#define GD32_CLOCK_TIMER10 GD32_CLOCK_CONFIG(APB2EN, 21U)
|
||||
#define GD32_CLOCK_USART5 GD32_CLOCK_CONFIG(APB2EN, 28U)
|
||||
#define GD32_CLOCK_SHRTIMER GD32_CLOCK_CONFIG(APB2EN, 29U)
|
||||
#define GD32_CLOCK_CMP GD32_CLOCK_CONFIG(APB2EN, 31U)
|
||||
|
||||
/* APB1 additional peripherals */
|
||||
#define GD32_CLOCK_CTC GD32_CLOCK_CONFIG(ADDAPB1EN, 27U)
|
||||
#define GD32_CLOCK_CAN2 GD32_CLOCK_CONFIG(ADDAPB1EN, 31U)
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32E50X_CLOCKS_H_ */
|
||||
71
include/zephyr/dt-bindings/clock/gd32f3x0-clocks.h
Normal file
71
include/zephyr/dt-bindings/clock/gd32f3x0-clocks.h
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Teslabs Engineering S.L.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F3X0_CLOCKS_H_
|
||||
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F3X0_CLOCKS_H_
|
||||
|
||||
#include "gd32-clocks-common.h"
|
||||
|
||||
/**
|
||||
* @name Register offsets
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GD32_AHBEN_OFFSET 0x14U
|
||||
#define GD32_APB1EN_OFFSET 0x1CU
|
||||
#define GD32_APB2EN_OFFSET 0x18U
|
||||
#define GD32_ADDAPB1EN_OFFSET 0xF8U
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Clock enable/disable definitions for peripherals
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* AHB peripherals */
|
||||
#define GD32_CLOCK_DMA GD32_CLOCK_CONFIG(AHBEN, 0U)
|
||||
#define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U)
|
||||
#define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U)
|
||||
#define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U)
|
||||
#define GD32_CLOCK_USBFS GD32_CLOCK_CONFIG(AHBEN, 12U)
|
||||
#define GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(AHBEN, 17U)
|
||||
#define GD32_CLOCK_GPIOB GD32_CLOCK_CONFIG(AHBEN, 18U)
|
||||
#define GD32_CLOCK_GPIOC GD32_CLOCK_CONFIG(AHBEN, 19U)
|
||||
#define GD32_CLOCK_GPIOD GD32_CLOCK_CONFIG(AHBEN, 20U)
|
||||
#define GD32_CLOCK_GPIOF GD32_CLOCK_CONFIG(AHBEN, 22U)
|
||||
#define GD32_CLOCK_TSI GD32_CLOCK_CONFIG(AHBEN, 24U)
|
||||
|
||||
/* APB1 peripherals */
|
||||
#define GD32_CLOCK_TIMER1 GD32_CLOCK_CONFIG(APB1EN, 0U)
|
||||
#define GD32_CLOCK_TIMER2 GD32_CLOCK_CONFIG(APB1EN, 1U)
|
||||
#define GD32_CLOCK_TIMER5 GD32_CLOCK_CONFIG(APB1EN, 4U)
|
||||
#define GD32_CLOCK_TIMER13 GD32_CLOCK_CONFIG(APB1EN, 8U)
|
||||
#define GD32_CLOCK_WWDGT GD32_CLOCK_CONFIG(APB1EN, 11U)
|
||||
#define GD32_CLOCK_SPI1 GD32_CLOCK_CONFIG(APB1EN, 14U)
|
||||
#define GD32_CLOCK_USART1 GD32_CLOCK_CONFIG(APB1EN, 17U)
|
||||
#define GD32_CLOCK_I2C0 GD32_CLOCK_CONFIG(APB1EN, 21U)
|
||||
#define GD32_CLOCK_I2C1 GD32_CLOCK_CONFIG(APB1EN, 22U)
|
||||
#define GD32_CLOCK_PMU GD32_CLOCK_CONFIG(APB1EN, 28U)
|
||||
#define GD32_CLOCK_DAC GD32_CLOCK_CONFIG(APB1EN, 29U)
|
||||
#define GD32_CLOCK_CEC GD32_CLOCK_CONFIG(APB1EN, 30U)
|
||||
|
||||
/* APB2 peripherals */
|
||||
#define GD32_CLOCK_CFGCMP GD32_CLOCK_CONFIG(APB2EN, 0U)
|
||||
#define GD32_CLOCK_ADC GD32_CLOCK_CONFIG(APB2EN, 9U)
|
||||
#define GD32_CLOCK_TIMER0 GD32_CLOCK_CONFIG(APB2EN, 11U)
|
||||
#define GD32_CLOCK_SPI0 GD32_CLOCK_CONFIG(APB2EN, 12U)
|
||||
#define GD32_CLOCK_USART0 GD32_CLOCK_CONFIG(APB2EN, 14U)
|
||||
#define GD32_CLOCK_TIMER14 GD32_CLOCK_CONFIG(APB2EN, 16U)
|
||||
#define GD32_CLOCK_TIMER15 GD32_CLOCK_CONFIG(APB2EN, 17U)
|
||||
#define GD32_CLOCK_TIMER16 GD32_CLOCK_CONFIG(APB2EN, 18U)
|
||||
|
||||
/* APB1 additional peripherals */
|
||||
#define GD32_CLOCK_CTC GD32_CLOCK_CONFIG(ADDAPB1EN, 27U)
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F3X0_CLOCKS_H_ */
|
||||
87
include/zephyr/dt-bindings/clock/gd32f403-clocks.h
Normal file
87
include/zephyr/dt-bindings/clock/gd32f403-clocks.h
Normal file
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Teslabs Engineering S.L.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F403_CLOCKS_H_
|
||||
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F403_CLOCKS_H_
|
||||
|
||||
#include "gd32-clocks-common.h"
|
||||
|
||||
/**
|
||||
* @name Register offsets
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GD32_AHBEN_OFFSET 0x14U
|
||||
#define GD32_APB1EN_OFFSET 0x1CU
|
||||
#define GD32_APB2EN_OFFSET 0x18U
|
||||
#define GD32_ADDAPB1EN_OFFSET 0xE4U
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Clock enable/disable definitions for peripherals
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* AHB peripherals */
|
||||
#define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHBEN, 0U)
|
||||
#define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHBEN, 1U)
|
||||
#define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U)
|
||||
#define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U)
|
||||
#define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U)
|
||||
#define GD32_CLOCK_EXMC GD32_CLOCK_CONFIG(AHBEN, 8U)
|
||||
#define GD32_CLOCK_SDIO GD32_CLOCK_CONFIG(AHBEN, 10U)
|
||||
#define GD32_CLOCK_USBFS GD32_CLOCK_CONFIG(AHBEN, 12U)
|
||||
|
||||
/* APB1 peripherals */
|
||||
#define GD32_CLOCK_TIMER2 GD32_CLOCK_CONFIG(APB1EN, 1U)
|
||||
#define GD32_CLOCK_TIMER3 GD32_CLOCK_CONFIG(APB1EN, 2U)
|
||||
#define GD32_CLOCK_TIMER5 GD32_CLOCK_CONFIG(APB1EN, 4U)
|
||||
#define GD32_CLOCK_TIMER6 GD32_CLOCK_CONFIG(APB1EN, 5U)
|
||||
#define GD32_CLOCK_TIMER11 GD32_CLOCK_CONFIG(APB1EN, 6U)
|
||||
#define GD32_CLOCK_TIMER12 GD32_CLOCK_CONFIG(APB1EN, 7U)
|
||||
#define GD32_CLOCK_TIMER13 GD32_CLOCK_CONFIG(APB1EN, 8U)
|
||||
#define GD32_CLOCK_WWDGT GD32_CLOCK_CONFIG(APB1EN, 11U)
|
||||
#define GD32_CLOCK_SPI1 GD32_CLOCK_CONFIG(APB1EN, 14U)
|
||||
#define GD32_CLOCK_SPI2 GD32_CLOCK_CONFIG(APB1EN, 15U)
|
||||
#define GD32_CLOCK_USART1 GD32_CLOCK_CONFIG(APB1EN, 17U)
|
||||
#define GD32_CLOCK_USART2 GD32_CLOCK_CONFIG(APB1EN, 18U)
|
||||
#define GD32_CLOCK_UART3 GD32_CLOCK_CONFIG(APB1EN, 19U)
|
||||
#define GD32_CLOCK_UART4 GD32_CLOCK_CONFIG(APB1EN, 20U)
|
||||
#define GD32_CLOCK_I2C0 GD32_CLOCK_CONFIG(APB1EN, 21U)
|
||||
#define GD32_CLOCK_I2C1 GD32_CLOCK_CONFIG(APB1EN, 22U)
|
||||
#define GD32_CLOCK_CAN0 GD32_CLOCK_CONFIG(APB1EN, 25U)
|
||||
#define GD32_CLOCK_CAN1 GD32_CLOCK_CONFIG(APB1EN, 26U)
|
||||
#define GD32_CLOCK_BKPI GD32_CLOCK_CONFIG(APB1EN, 27U)
|
||||
#define GD32_CLOCK_PMU GD32_CLOCK_CONFIG(APB1EN, 28U)
|
||||
#define GD32_CLOCK_DAC GD32_CLOCK_CONFIG(APB1EN, 29U)
|
||||
|
||||
/* APB2 peripherals */
|
||||
#define GD32_CLOCK_AFIO GD32_CLOCK_CONFIG(APB2EN, 0U)
|
||||
#define GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(APB2EN, 2U)
|
||||
#define GD32_CLOCK_GPIOB GD32_CLOCK_CONFIG(APB2EN, 3U)
|
||||
#define GD32_CLOCK_GPIOC GD32_CLOCK_CONFIG(APB2EN, 4U)
|
||||
#define GD32_CLOCK_GPIOD GD32_CLOCK_CONFIG(APB2EN, 5U)
|
||||
#define GD32_CLOCK_GPIOE GD32_CLOCK_CONFIG(APB2EN, 6U)
|
||||
#define GD32_CLOCK_GPIOF GD32_CLOCK_CONFIG(APB2EN, 7U)
|
||||
#define GD32_CLOCK_GPIOG GD32_CLOCK_CONFIG(APB2EN, 8U)
|
||||
#define GD32_CLOCK_ADC0 GD32_CLOCK_CONFIG(APB2EN, 9U)
|
||||
#define GD32_CLOCK_ADC1 GD32_CLOCK_CONFIG(APB2EN, 10U)
|
||||
#define GD32_CLOCK_TIMER0 GD32_CLOCK_CONFIG(APB2EN, 11U)
|
||||
#define GD32_CLOCK_SPI0 GD32_CLOCK_CONFIG(APB2EN, 12U)
|
||||
#define GD32_CLOCK_TIMER7 GD32_CLOCK_CONFIG(APB2EN, 13U)
|
||||
#define GD32_CLOCK_USART0 GD32_CLOCK_CONFIG(APB2EN, 14U)
|
||||
#define GD32_CLOCK_ADC2 GD32_CLOCK_CONFIG(APB2EN, 15U)
|
||||
#define GD32_CLOCK_TIMER8 GD32_CLOCK_CONFIG(APB2EN, 19U)
|
||||
#define GD32_CLOCK_TIMER9 GD32_CLOCK_CONFIG(APB2EN, 20U)
|
||||
#define GD32_CLOCK_TIMER10 GD32_CLOCK_CONFIG(APB2EN, 21U)
|
||||
|
||||
/* APB1 additional peripherals */
|
||||
#define GD32_CLOCK_CTC GD32_CLOCK_CONFIG(ADDAPB1EN, 27U)
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F403_CLOCKS_H_ */
|
||||
115
include/zephyr/dt-bindings/clock/gd32f4xx-clocks.h
Normal file
115
include/zephyr/dt-bindings/clock/gd32f4xx-clocks.h
Normal file
|
|
@ -0,0 +1,115 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Teslabs Engineering S.L.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F4XX_CLOCKS_H_
|
||||
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F4XX_CLOCKS_H_
|
||||
|
||||
#include "gd32-clocks-common.h"
|
||||
|
||||
/**
|
||||
* @name Register offsets
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GD32_AHB1EN_OFFSET 0x30U
|
||||
#define GD32_AHB2EN_OFFSET 0x34U
|
||||
#define GD32_AHB3EN_OFFSET 0x38U
|
||||
#define GD32_APB1EN_OFFSET 0x40U
|
||||
#define GD32_APB2EN_OFFSET 0x44U
|
||||
#define GD32_ADDAPB1EN_OFFSET 0xE4U
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Clock enable/disable definitions for peripherals
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* AHB1 peripherals */
|
||||
#define GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(AHB1EN, 0U)
|
||||
#define GD32_CLOCK_GPIOB GD32_CLOCK_CONFIG(AHB1EN, 1U)
|
||||
#define GD32_CLOCK_GPIOC GD32_CLOCK_CONFIG(AHB1EN, 2U)
|
||||
#define GD32_CLOCK_GPIOD GD32_CLOCK_CONFIG(AHB1EN, 3U)
|
||||
#define GD32_CLOCK_GPIOE GD32_CLOCK_CONFIG(AHB1EN, 4U)
|
||||
#define GD32_CLOCK_GPIOF GD32_CLOCK_CONFIG(AHB1EN, 5U)
|
||||
#define GD32_CLOCK_GPIOG GD32_CLOCK_CONFIG(AHB1EN, 6U)
|
||||
#define GD32_CLOCK_GPIOH GD32_CLOCK_CONFIG(AHB1EN, 7U)
|
||||
#define GD32_CLOCK_GPIOI GD32_CLOCK_CONFIG(AHB1EN, 8U)
|
||||
#define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHB1EN, 12U)
|
||||
#define GD32_CLOCK_BKPSRAM GD32_CLOCK_CONFIG(AHB1EN, 18U)
|
||||
#define GD32_CLOCK_TCMSRAM GD32_CLOCK_CONFIG(AHB1EN, 20U)
|
||||
#define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHB1EN, 21U)
|
||||
#define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHB1EN, 22U)
|
||||
#define GD32_CLOCK_IPA GD32_CLOCK_CONFIG(AHB1EN, 23U)
|
||||
#define GD32_CLOCK_ENET GD32_CLOCK_CONFIG(AHB1EN, 25U)
|
||||
#define GD32_CLOCK_ENETTX GD32_CLOCK_CONFIG(AHB1EN, 26U)
|
||||
#define GD32_CLOCK_ENETRX GD32_CLOCK_CONFIG(AHB1EN, 27U)
|
||||
#define GD32_CLOCK_ENETPTP GD32_CLOCK_CONFIG(AHB1EN, 28U)
|
||||
#define GD32_CLOCK_USBHS GD32_CLOCK_CONFIG(AHB1EN, 29U)
|
||||
#define GD32_CLOCK_USBHSULPI GD32_CLOCK_CONFIG(AHB1EN, 30U)
|
||||
|
||||
/* AHB2 peripherals */
|
||||
#define GD32_CLOCK_DCI GD32_CLOCK_CONFIG(AHB2EN, 0U)
|
||||
#define GD32_CLOCK_TRNG GD32_CLOCK_CONFIG(AHB2EN, 6U)
|
||||
#define GD32_CLOCK_USBFS GD32_CLOCK_CONFIG(AHB2EN, 7U)
|
||||
|
||||
/* AHB3 peripherals */
|
||||
#define GD32_CLOCK_EXMC GD32_CLOCK_CONFIG(AHB3EN, 0U)
|
||||
|
||||
/* APB1 peripherals */
|
||||
#define GD32_CLOCK_TIMER1 GD32_CLOCK_CONFIG(APB1EN, 0U)
|
||||
#define GD32_CLOCK_TIMER2 GD32_CLOCK_CONFIG(APB1EN, 1U)
|
||||
#define GD32_CLOCK_TIMER3 GD32_CLOCK_CONFIG(APB1EN, 2U)
|
||||
#define GD32_CLOCK_TIMER4 GD32_CLOCK_CONFIG(APB1EN, 3U)
|
||||
#define GD32_CLOCK_TIMER5 GD32_CLOCK_CONFIG(APB1EN, 4U)
|
||||
#define GD32_CLOCK_TIMER6 GD32_CLOCK_CONFIG(APB1EN, 5U)
|
||||
#define GD32_CLOCK_TIMER11 GD32_CLOCK_CONFIG(APB1EN, 6U)
|
||||
#define GD32_CLOCK_TIMER12 GD32_CLOCK_CONFIG(APB1EN, 7U)
|
||||
#define GD32_CLOCK_TIMER13 GD32_CLOCK_CONFIG(APB1EN, 8U)
|
||||
#define GD32_CLOCK_WWDGT GD32_CLOCK_CONFIG(APB1EN, 11U)
|
||||
#define GD32_CLOCK_SPI1 GD32_CLOCK_CONFIG(APB1EN, 14U)
|
||||
#define GD32_CLOCK_SPI2 GD32_CLOCK_CONFIG(APB1EN, 15U)
|
||||
#define GD32_CLOCK_USART1 GD32_CLOCK_CONFIG(APB1EN, 17U)
|
||||
#define GD32_CLOCK_USART2 GD32_CLOCK_CONFIG(APB1EN, 18U)
|
||||
#define GD32_CLOCK_UART3 GD32_CLOCK_CONFIG(APB1EN, 19U)
|
||||
#define GD32_CLOCK_UART4 GD32_CLOCK_CONFIG(APB1EN, 20U)
|
||||
#define GD32_CLOCK_I2C0 GD32_CLOCK_CONFIG(APB1EN, 21U)
|
||||
#define GD32_CLOCK_I2C1 GD32_CLOCK_CONFIG(APB1EN, 22U)
|
||||
#define GD32_CLOCK_I2C2 GD32_CLOCK_CONFIG(APB1EN, 23U)
|
||||
#define GD32_CLOCK_CAN0 GD32_CLOCK_CONFIG(APB1EN, 25U)
|
||||
#define GD32_CLOCK_CAN1 GD32_CLOCK_CONFIG(APB1EN, 26U)
|
||||
#define GD32_CLOCK_PMU GD32_CLOCK_CONFIG(APB1EN, 28U)
|
||||
#define GD32_CLOCK_DAC GD32_CLOCK_CONFIG(APB1EN, 29U)
|
||||
#define GD32_CLOCK_UART6 GD32_CLOCK_CONFIG(APB1EN, 30U)
|
||||
#define GD32_CLOCK_UART7 GD32_CLOCK_CONFIG(APB1EN, 31U)
|
||||
#define GD32_CLOCK_RTC GD32_CLOCK_CONFIG(BDCTL, 15U)
|
||||
|
||||
/* APB2 peripherals */
|
||||
#define GD32_CLOCK_TIMER0 GD32_CLOCK_CONFIG(APB2EN, 0U)
|
||||
#define GD32_CLOCK_TIMER7 GD32_CLOCK_CONFIG(APB2EN, 1U)
|
||||
#define GD32_CLOCK_USART0 GD32_CLOCK_CONFIG(APB2EN, 4U)
|
||||
#define GD32_CLOCK_USART5 GD32_CLOCK_CONFIG(APB2EN, 5U)
|
||||
#define GD32_CLOCK_ADC0 GD32_CLOCK_CONFIG(APB2EN, 8U)
|
||||
#define GD32_CLOCK_ADC1 GD32_CLOCK_CONFIG(APB2EN, 9U)
|
||||
#define GD32_CLOCK_ADC2 GD32_CLOCK_CONFIG(APB2EN, 10U)
|
||||
#define GD32_CLOCK_SDIO GD32_CLOCK_CONFIG(APB2EN, 11U)
|
||||
#define GD32_CLOCK_SPI0 GD32_CLOCK_CONFIG(APB2EN, 12U)
|
||||
#define GD32_CLOCK_SPI3 GD32_CLOCK_CONFIG(APB2EN, 13U)
|
||||
#define GD32_CLOCK_SYSCFG GD32_CLOCK_CONFIG(APB2EN, 14U)
|
||||
#define GD32_CLOCK_TIMER8 GD32_CLOCK_CONFIG(APB2EN, 16U)
|
||||
#define GD32_CLOCK_TIMER9 GD32_CLOCK_CONFIG(APB2EN, 17U)
|
||||
#define GD32_CLOCK_TIMER10 GD32_CLOCK_CONFIG(APB2EN, 18U)
|
||||
#define GD32_CLOCK_SPI4 GD32_CLOCK_CONFIG(APB2EN, 20U)
|
||||
#define GD32_CLOCK_SPI5 GD32_CLOCK_CONFIG(APB2EN, 21U)
|
||||
#define GD32_CLOCK_TLI GD32_CLOCK_CONFIG(APB2EN, 26U)
|
||||
|
||||
/* APB1 additional peripherals */
|
||||
#define GD32_CLOCK_CTC GD32_CLOCK_CONFIG(ADDAPB1EN, 27U)
|
||||
#define GD32_CLOCK_IREF GD32_CLOCK_CONFIG(ADDAPB1EN, 31U)
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32F4XX_CLOCKS_H_ */
|
||||
74
include/zephyr/dt-bindings/clock/gd32vf103-clocks.h
Normal file
74
include/zephyr/dt-bindings/clock/gd32vf103-clocks.h
Normal file
|
|
@ -0,0 +1,74 @@
|
|||
/*
|
||||
* Copyright (c) 2022 Teslabs Engineering S.L.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32VF103_CLOCKS_H_
|
||||
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32VF103_CLOCKS_H_
|
||||
|
||||
#include "gd32-clocks-common.h"
|
||||
|
||||
/**
|
||||
* @name Register offsets
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GD32_AHBEN_OFFSET 0x14U
|
||||
#define GD32_APB1EN_OFFSET 0x1CU
|
||||
#define GD32_APB2EN_OFFSET 0x18U
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @name Clock enable/disable definitions for peripherals
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* AHB peripherals */
|
||||
#define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHBEN, 0U)
|
||||
#define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHBEN, 1U)
|
||||
#define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U)
|
||||
#define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U)
|
||||
#define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U)
|
||||
#define GD32_CLOCK_EXMC GD32_CLOCK_CONFIG(AHBEN, 8U)
|
||||
#define GD32_CLOCK_USBFS GD32_CLOCK_CONFIG(AHBEN, 12U)
|
||||
|
||||
/* APB1 peripherals */
|
||||
#define GD32_CLOCK_TIMER1 GD32_CLOCK_CONFIG(APB1EN, 0U)
|
||||
#define GD32_CLOCK_TIMER2 GD32_CLOCK_CONFIG(APB1EN, 1U)
|
||||
#define GD32_CLOCK_TIMER3 GD32_CLOCK_CONFIG(APB1EN, 2U)
|
||||
#define GD32_CLOCK_TIMER4 GD32_CLOCK_CONFIG(APB1EN, 3U)
|
||||
#define GD32_CLOCK_TIMER5 GD32_CLOCK_CONFIG(APB1EN, 4U)
|
||||
#define GD32_CLOCK_TIMER6 GD32_CLOCK_CONFIG(APB1EN, 5U)
|
||||
#define GD32_CLOCK_WWDGT GD32_CLOCK_CONFIG(APB1EN, 11U)
|
||||
#define GD32_CLOCK_SPI1 GD32_CLOCK_CONFIG(APB1EN, 14U)
|
||||
#define GD32_CLOCK_SPI2 GD32_CLOCK_CONFIG(APB1EN, 15U)
|
||||
#define GD32_CLOCK_USART1 GD32_CLOCK_CONFIG(APB1EN, 17U)
|
||||
#define GD32_CLOCK_USART2 GD32_CLOCK_CONFIG(APB1EN, 18U)
|
||||
#define GD32_CLOCK_UART3 GD32_CLOCK_CONFIG(APB1EN, 19U)
|
||||
#define GD32_CLOCK_UART4 GD32_CLOCK_CONFIG(APB1EN, 20U)
|
||||
#define GD32_CLOCK_I2C0 GD32_CLOCK_CONFIG(APB1EN, 21U)
|
||||
#define GD32_CLOCK_I2C1 GD32_CLOCK_CONFIG(APB1EN, 22U)
|
||||
#define GD32_CLOCK_CAN0 GD32_CLOCK_CONFIG(APB1EN, 25U)
|
||||
#define GD32_CLOCK_CAN1 GD32_CLOCK_CONFIG(APB1EN, 26U)
|
||||
#define GD32_CLOCK_BKPI GD32_CLOCK_CONFIG(APB1EN, 27U)
|
||||
#define GD32_CLOCK_PMU GD32_CLOCK_CONFIG(APB1EN, 28U)
|
||||
#define GD32_CLOCK_DAC GD32_CLOCK_CONFIG(APB1EN, 29U)
|
||||
|
||||
/* APB2 peripherals */
|
||||
#define GD32_CLOCK_AFIO GD32_CLOCK_CONFIG(APB2EN, 0U)
|
||||
#define GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(APB2EN, 2U)
|
||||
#define GD32_CLOCK_GPIOB GD32_CLOCK_CONFIG(APB2EN, 3U)
|
||||
#define GD32_CLOCK_GPIOC GD32_CLOCK_CONFIG(APB2EN, 4U)
|
||||
#define GD32_CLOCK_GPIOD GD32_CLOCK_CONFIG(APB2EN, 5U)
|
||||
#define GD32_CLOCK_GPIOE GD32_CLOCK_CONFIG(APB2EN, 6U)
|
||||
#define GD32_CLOCK_ADC0 GD32_CLOCK_CONFIG(APB2EN, 9U)
|
||||
#define GD32_CLOCK_ADC1 GD32_CLOCK_CONFIG(APB2EN, 10U)
|
||||
#define GD32_CLOCK_TIMER0 GD32_CLOCK_CONFIG(APB2EN, 11U)
|
||||
#define GD32_CLOCK_SPI0 GD32_CLOCK_CONFIG(APB2EN, 12U)
|
||||
#define GD32_CLOCK_USART0 GD32_CLOCK_CONFIG(APB2EN, 14U)
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_GD32VF103_CLOCKS_H_ */
|
||||
25
soc/arm/gigadevice/gd32e10x/gd32_regs.h
Normal file
25
soc/arm/gigadevice/gd32e10x/gd32_regs.h
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* Copyright (c) 2022, Teslabs Engineering S.L.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef SOC_ARM_GIGADEVICE_GD32E50X_GD32_REGS_H_
|
||||
#define SOC_ARM_GIGADEVICE_GD32E50X_GD32_REGS_H_
|
||||
|
||||
#include <zephyr/sys/util_macro.h>
|
||||
|
||||
/* RCU */
|
||||
#define RCU_CFG0_OFFSET 0x04U
|
||||
#define RCU_AHBEN_OFFSET 0x14U
|
||||
#define RCU_APB2EN_OFFSET 0x18U
|
||||
#define RCU_APB1EN_OFFSET 0x1CU
|
||||
#define RCU_ADDAPB1EN_OFFSET 0xE4U
|
||||
|
||||
#define RCU_CFG0_AHBPSC_POS 4U
|
||||
#define RCU_CFG0_AHBPSC_MSK (BIT_MASK(4) << RCU_CFG0_AHBPSC_POS)
|
||||
#define RCU_CFG0_APB1PSC_POS 8U
|
||||
#define RCU_CFG0_APB1PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB1PSC_POS)
|
||||
#define RCU_CFG0_APB2PSC_POS 11U
|
||||
#define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS)
|
||||
|
||||
#endif /* SOC_ARM_GIGADEVICE_GD32E50X_GD32_REGS_H_ */
|
||||
25
soc/arm/gigadevice/gd32e50x/gd32_regs.h
Normal file
25
soc/arm/gigadevice/gd32e50x/gd32_regs.h
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* Copyright (c) 2022, Teslabs Engineering S.L.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef SOC_ARM_GIGADEVICE_GD32E50X_GD32_REGS_H_
|
||||
#define SOC_ARM_GIGADEVICE_GD32E50X_GD32_REGS_H_
|
||||
|
||||
#include <zephyr/sys/util_macro.h>
|
||||
|
||||
/* RCU */
|
||||
#define RCU_CFG0_OFFSET 0x04U
|
||||
#define RCU_AHBEN_OFFSET 0x14U
|
||||
#define RCU_APB2EN_OFFSET 0x18U
|
||||
#define RCU_APB1EN_OFFSET 0x1CU
|
||||
#define RCU_ADDAPB1EN_OFFSET 0xE4U
|
||||
|
||||
#define RCU_CFG0_AHBPSC_POS 4U
|
||||
#define RCU_CFG0_AHBPSC_MSK (BIT_MASK(4) << RCU_CFG0_AHBPSC_POS)
|
||||
#define RCU_CFG0_APB1PSC_POS 8U
|
||||
#define RCU_CFG0_APB1PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB1PSC_POS)
|
||||
#define RCU_CFG0_APB2PSC_POS 11U
|
||||
#define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS)
|
||||
|
||||
#endif /* SOC_ARM_GIGADEVICE_GD32E50X_GD32_REGS_H_ */
|
||||
25
soc/arm/gigadevice/gd32f3x0/gd32_regs.h
Normal file
25
soc/arm/gigadevice/gd32f3x0/gd32_regs.h
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* Copyright (c) 2022, Teslabs Engineering S.L.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef SOC_ARM_GIGADEVICE_GD32F3X0_GD32_REGS_H_
|
||||
#define SOC_ARM_GIGADEVICE_GD32F3X0_GD32_REGS_H_
|
||||
|
||||
#include <zephyr/sys/util_macro.h>
|
||||
|
||||
/* RCU */
|
||||
#define RCU_CFG0_OFFSET 0x04U
|
||||
#define RCU_AHBEN_OFFSET 0x14U
|
||||
#define RCU_APB2EN_OFFSET 0x18U
|
||||
#define RCU_APB1EN_OFFSET 0x1CU
|
||||
#define RCU_ADDAPB1EN_OFFSET 0xF8U
|
||||
|
||||
#define RCU_CFG0_AHBPSC_POS 4U
|
||||
#define RCU_CFG0_AHBPSC_MSK (BIT_MASK(4) << RCU_CFG0_AHBPSC_POS)
|
||||
#define RCU_CFG0_APB1PSC_POS 8U
|
||||
#define RCU_CFG0_APB1PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB1PSC_POS)
|
||||
#define RCU_CFG0_APB2PSC_POS 11U
|
||||
#define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS)
|
||||
|
||||
#endif /* SOC_ARM_GIGADEVICE_GD32F3X0_GD32_REGS_H_ */
|
||||
25
soc/arm/gigadevice/gd32f403/gd32_regs.h
Normal file
25
soc/arm/gigadevice/gd32f403/gd32_regs.h
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* Copyright (c) 2022, Teslabs Engineering S.L.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef SOC_ARM_GIGADEVICE_GD32F403_GD32_REGS_H_
|
||||
#define SOC_ARM_GIGADEVICE_GD32F403_GD32_REGS_H_
|
||||
|
||||
#include <zephyr/sys/util_macro.h>
|
||||
|
||||
/* RCU */
|
||||
#define RCU_CFG0_OFFSET 0x04U
|
||||
#define RCU_AHBEN_OFFSET 0x14U
|
||||
#define RCU_APB2EN_OFFSET 0x18U
|
||||
#define RCU_APB1EN_OFFSET 0x1CU
|
||||
#define RCU_ADDAPB1EN_OFFSET 0xE4U
|
||||
|
||||
#define RCU_CFG0_AHBPSC_POS 4U
|
||||
#define RCU_CFG0_AHBPSC_MSK (BIT_MASK(4) << RCU_CFG0_AHBPSC_POS)
|
||||
#define RCU_CFG0_APB1PSC_POS 8U
|
||||
#define RCU_CFG0_APB1PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB1PSC_POS)
|
||||
#define RCU_CFG0_APB2PSC_POS 11U
|
||||
#define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS)
|
||||
|
||||
#endif /* SOC_ARM_GIGADEVICE_GD32F403_GD32_REGS_H_ */
|
||||
27
soc/arm/gigadevice/gd32f4xx/gd32_regs.h
Normal file
27
soc/arm/gigadevice/gd32f4xx/gd32_regs.h
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
/*
|
||||
* Copyright (c) 2022, Teslabs Engineering S.L.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef SOC_ARM_GIGADEVICE_GD32F4XX_GD32_REGS_H_
|
||||
#define SOC_ARM_GIGADEVICE_GD32F4XX_GD32_REGS_H_
|
||||
|
||||
#include <zephyr/sys/util_macro.h>
|
||||
|
||||
/* RCU */
|
||||
#define RCU_CFG0_OFFSET 0x08U
|
||||
#define RCU_AHB1EN_OFFSET 0x30U
|
||||
#define RCU_AHB2EN_OFFSET 0x34U
|
||||
#define RCU_AHB3EN_OFFSET 0x38U
|
||||
#define RCU_APB1EN_OFFSET 0x40U
|
||||
#define RCU_APB2EN_OFFSET 0x44U
|
||||
#define RCU_ADDAPB1EN_OFFSET 0xE4U
|
||||
|
||||
#define RCU_CFG0_AHBPSC_POS 4U
|
||||
#define RCU_CFG0_AHBPSC_MSK (BIT_MASK(4) << RCU_CFG0_AHBPSC_POS)
|
||||
#define RCU_CFG0_APB1PSC_POS 10U
|
||||
#define RCU_CFG0_APB1PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB1PSC_POS)
|
||||
#define RCU_CFG0_APB2PSC_POS 13U
|
||||
#define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS)
|
||||
|
||||
#endif /* SOC_ARM_GIGADEVICE_GD32F4XX_GD32_REGS_H_ */
|
||||
25
soc/riscv/riscv-privilege/gd32vf103/gd32_regs.h
Normal file
25
soc/riscv/riscv-privilege/gd32vf103/gd32_regs.h
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* Copyright (c) 2022, Teslabs Engineering S.L.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef SOC_ARM_GIGADEVICE_GD32VF103_GD32_REGS_H_
|
||||
#define SOC_ARM_GIGADEVICE_GD32VF103_GD32_REGS_H_
|
||||
|
||||
#include <zephyr/sys/util_macro.h>
|
||||
|
||||
/* RCU */
|
||||
#define RCU_CFG0_OFFSET 0x04U
|
||||
#define RCU_AHBEN_OFFSET 0x14U
|
||||
#define RCU_APB2EN_OFFSET 0x18U
|
||||
#define RCU_APB1EN_OFFSET 0x1CU
|
||||
#define RCU_ADDAPB1EN_OFFSET 0xE4U
|
||||
|
||||
#define RCU_CFG0_AHBPSC_POS 4U
|
||||
#define RCU_CFG0_AHBPSC_MSK (BIT_MASK(4) << RCU_CFG0_AHBPSC_POS)
|
||||
#define RCU_CFG0_APB1PSC_POS 8U
|
||||
#define RCU_CFG0_APB1PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB1PSC_POS)
|
||||
#define RCU_CFG0_APB2PSC_POS 11U
|
||||
#define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS)
|
||||
|
||||
#endif /* SOC_ARM_GIGADEVICE_GD32E50X_GD32_REGS_H_ */
|
||||
Loading…
Reference in a new issue