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boards: arm: enabling hsi48 for RNG peripheral on stm32 platforms

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The different boards with stm32 which have node enabled in their DTS
also requires the HSI48 clock to be enabled.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
Francois Ramu 2022-11-24 13:58:31 +01:00 committed by Fabio Baltieri
parent b3ccd3abc6
commit 4f42512d8e
14 changed files with 56 additions and 0 deletions
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4
boards/arm/b_l072z_lrwan1/b_l072z_lrwan1.dts
View file

@ -75,6 +75,10 @@
status = "okay";
};
&clk_hsi48 {
status = "okay";
};
&clk_hsi {
status = "okay";
};

4
boards/arm/b_l4s5i_iot01a/b_l4s5i_iot01a.dts
View file

@ -55,6 +55,10 @@
status = "okay";
};
&clk_hsi48 {
status = "okay";
};
&clk_hsi {
status = "okay";
};

4
boards/arm/b_u585i_iot02a/b_u585i_iot02a-common.dtsi
View file

@ -56,6 +56,10 @@
};
};
&clk_hsi48 {
status = "okay";
};
&clk_lse {
status = "okay";
};

4
boards/arm/nucleo_g474re/nucleo_g474re.dts
View file

@ -57,6 +57,10 @@
status = "okay";
};
&clk_hsi48 {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(24)>;
status = "okay";

4
boards/arm/nucleo_h723zg/nucleo_h723zg.dts
View file

@ -66,6 +66,10 @@
status = "okay";
};
&clk_hsi48 {
status = "okay";
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */

4
boards/arm/nucleo_h743zi/nucleo_h743zi.dts
View file

@ -64,6 +64,10 @@
status = "okay";
};
&clk_hsi48 {
status = "okay";
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */

4
boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m7.dts
View file

@ -49,6 +49,10 @@
status = "okay";
};
&clk_hsi48 {
status = "okay";
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */

4
boards/arm/nucleo_h753zi/nucleo_h753zi.dts
View file

@ -63,6 +63,10 @@
status = "okay";
};
&clk_hsi48 {
status = "okay";
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */

4
boards/arm/nucleo_h7a3zi_q/nucleo_h7a3zi_q.dts
View file

@ -58,6 +58,10 @@
};
};
&clk_hsi48 {
status = "okay";
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */

4
boards/arm/nucleo_l073rz/nucleo_l073rz.dts
View file

@ -79,6 +79,10 @@
status = "okay";
};
&clk_hsi48 {
status = "okay";
};
&pll {
div = <2>;
mul = <8>;

4
boards/arm/nucleo_l552ze_q/nucleo_l552ze_q-common.dtsi
View file

@ -34,6 +34,10 @@
};
};
&clk_hsi48 {
status = "okay";
};
&clk_msi {
status = "okay";
msi-range = <6>;

4
boards/arm/nucleo_u575zi_q/nucleo_u575zi_q-common.dtsi
View file

@ -34,6 +34,10 @@
};
};
&clk_hsi48 {
status = "okay";
};
&clk_lse {
status = "okay";
};

4
boards/arm/stm32h747i_disco/stm32h747i_disco_m7.dts
View file

@ -55,6 +55,10 @@
status = "okay";
};
&clk_hsi48 {
status = "okay";
};
&pll {
div-m = <5>;
mul-n = <160>;

4
boards/arm/stm32l562e_dk/stm32l562e_dk_common.dtsi
View file

@ -59,6 +59,10 @@
cpu-power-states = <&stop0 &stop1 &stop2>;
};
&clk_hsi48 {
status = "okay";
};
&clk_msi {
status = "okay";
msi-range = <6>;