dts: st: Add all missing l010 SoCs
Add minimal devicetree entries to enable the whole stm32l010 SoC family. Signed-off-by: Gerson Fernando Budke <gerson.budke@ossystems.com.br>
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dts/arm/st/l0/stm32l010X4.dtsi
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dts/arm/st/l0/stm32l010X4.dtsi
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/*
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* Copyright (c) 2023 OS Systems
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <st/l0/stm32l010.dtsi>
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/ {
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sram0: memory@20000000 {
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reg = <0x20000000 DT_SIZE_K(2)>;
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};
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soc {
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eeprom: eeprom@8080000{
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reg = <0x08080000 128>;
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};
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flash-controller@40022000 {
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flash0: flash@8000000 {
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reg = <0x08000000 DT_SIZE_K(16)>;
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};
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};
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};
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};
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dts/arm/st/l0/stm32l010X6.dtsi
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dts/arm/st/l0/stm32l010X6.dtsi
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/*
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* Copyright (c) 2023 OS Systems
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <st/l0/stm32l010.dtsi>
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/ {
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sram0: memory@20000000 {
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reg = <0x20000000 DT_SIZE_K(8)>;
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};
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soc {
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eeprom: eeprom@8080000{
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reg = <0x08080000 256>;
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};
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flash-controller@40022000 {
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flash0: flash@8000000 {
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reg = <0x08000000 DT_SIZE_K(32)>;
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};
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};
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};
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};
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dts/arm/st/l0/stm32l010X8.dtsi
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dts/arm/st/l0/stm32l010X8.dtsi
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/*
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* Copyright (c) 2023 OS Systems
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <st/l0/stm32l010.dtsi>
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/ {
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sram0: memory@20000000 {
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reg = <0x20000000 DT_SIZE_K(8)>;
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};
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soc {
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eeprom: eeprom@8080000{
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reg = <0x08080000 256>;
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};
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flash-controller@40022000 {
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flash0: flash@8000000 {
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reg = <0x08000000 DT_SIZE_K(64)>;
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};
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};
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};
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};
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