dts: st: Add all missing l010 SoCs

Add minimal devicetree entries to enable the whole stm32l010
SoC family.

Signed-off-by: Gerson Fernando Budke <gerson.budke@ossystems.com.br>
This commit is contained in:
Gerson Fernando Budke 2023-10-16 14:51:10 +02:00 committed by Carles Cufí
parent 88c9d1fbaf
commit 5067e543fa
3 changed files with 78 additions and 0 deletions

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/*
* Copyright (c) 2023 OS Systems
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/l0/stm32l010.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(2)>;
};
soc {
eeprom: eeprom@8080000{
reg = <0x08080000 128>;
};
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(16)>;
};
};
};
};

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/*
* Copyright (c) 2023 OS Systems
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/l0/stm32l010.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(8)>;
};
soc {
eeprom: eeprom@8080000{
reg = <0x08080000 256>;
};
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(32)>;
};
};
};
};

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/*
* Copyright (c) 2023 OS Systems
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/l0/stm32l010.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(8)>;
};
soc {
eeprom: eeprom@8080000{
reg = <0x08080000 256>;
};
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(64)>;
};
};
};
};