drivers: clock_control: add NXP S32 driver

The clock controller is a singleton controller for all the system-level
clocks (XOSC, PLL, CGM, etc) to provide run-time information to the
peripheral device drivers about the module's clocks.
Clock configuration is not yet supported.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>

drivers/clock_control/CMakeLists.txt

@@ -25,6 +25,7 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_INFINEON_CAT1       clock_cont
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SAM                 clock_control_sam_pmc.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SMARTBOND           clock_control_smartbond.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NUMAKER_SCC         clock_control_numaker_scc.c)
+zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NXP_S32             clock_control_nxp_s32.c)
 
 
 if(CONFIG_CLOCK_CONTROL_STM32_CUBE)

drivers/clock_control/Kconfig

@@ -76,4 +76,6 @@ source "drivers/clock_control/Kconfig.smartbond"
 
 source "drivers/clock_control/Kconfig.numaker"
 
+source "drivers/clock_control/Kconfig.nxp_s32"
+
 endif # CLOCK_CONTROL

drivers/clock_control/Kconfig.nxp_s32

@@ -0,0 +1,20 @@
+# Copyright 2023 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config CLOCK_CONTROL_NXP_S32
+	bool "NXP S32 clock control driver"
+	default y
+	depends on DT_HAS_NXP_S32_CLOCK_ENABLED
+	help
+	  Enable support for NXP S32 clock control driver.
+
+if CLOCK_CONTROL_NXP_S32
+
+config CLOCK_CONTROL_NXP_S32_CLOCK_CONFIG_IDX
+	int
+	default 0
+	help
+	  This option specifies the zero-based index of the clock configuration
+	  used to initialize the SoC clocks.
+
+endif # CLOCK_CONTROL_NXP_S32

drivers/clock_control/clock_control_nxp_s32.c

@@ -0,0 +1,80 @@
+/*
+ * Copyright 2023 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT nxp_s32_clock
+
+#include <zephyr/drivers/clock_control.h>
+
+#include <Clock_Ip.h>
+
+#define NXP_S32_CLOCK_CONFIG_IDX CONFIG_CLOCK_CONTROL_NXP_S32_CLOCK_CONFIG_IDX
+
+BUILD_ASSERT(CLOCK_IP_GET_FREQUENCY_API == STD_ON,
+	     "Clock Get Frequency API must be enabled");
+
+static int nxp_s32_clock_on(const struct device *dev,
+			    clock_control_subsys_t sub_system)
+{
+	Clock_Ip_NameType clock_name = (Clock_Ip_NameType)sub_system;
+
+	if ((clock_name <= CLOCK_IS_OFF) || (clock_name >= RESERVED_CLK)) {
+		return -EINVAL;
+	}
+
+	Clock_Ip_EnableModuleClock(clock_name);
+
+	return 0;
+}
+
+static int nxp_s32_clock_off(const struct device *dev,
+			     clock_control_subsys_t sub_system)
+{
+	Clock_Ip_NameType clock_name = (Clock_Ip_NameType)sub_system;
+
+	if ((clock_name <= CLOCK_IS_OFF) || (clock_name >= RESERVED_CLK)) {
+		return -EINVAL;
+	}
+
+	Clock_Ip_DisableModuleClock(clock_name);
+
+	return 0;
+}
+
+static int nxp_s32_clock_get_rate(const struct device *dev,
+				  clock_control_subsys_t sub_system,
+				  uint32_t *rate)
+{
+	Clock_Ip_NameType clock_name = (Clock_Ip_NameType)sub_system;
+
+	if ((clock_name <= CLOCK_IS_OFF) || (clock_name >= RESERVED_CLK)) {
+		return -EINVAL;
+	}
+
+	*rate = Clock_Ip_GetClockFrequency(clock_name);
+
+	return 0;
+}
+
+static int nxp_s32_clock_init(const struct device *dev)
+{
+	Clock_Ip_StatusType status;
+
+	status = Clock_Ip_Init(&Clock_Ip_aClockConfig[NXP_S32_CLOCK_CONFIG_IDX]);
+
+	return (status == CLOCK_IP_SUCCESS ? 0 : -EIO);
+}
+
+static const struct clock_control_driver_api nxp_s32_clock_driver_api = {
+	.on = nxp_s32_clock_on,
+	.off = nxp_s32_clock_off,
+	.get_rate = nxp_s32_clock_get_rate,
+};
+
+DEVICE_DT_INST_DEFINE(0,
+		      &nxp_s32_clock_init,
+		      NULL, NULL, NULL,
+		      PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
+		      &nxp_s32_clock_driver_api);

dts/bindings/clock/nxp,s32-clock.yaml

@@ -0,0 +1,18 @@
+# Copyright 2023 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP S32 clock generator IP node
+
+compatible: "nxp,s32-clock"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+  reg:
+    required: true
+
+  "#clock-cells":
+    const: 1
+
+clock-cells:
+  - name