drivers: clock: rcar: Add r8a779f0 support

Add support of r8a779f0 cpg driver.
r8a779f0 soc has its own clock tree.
Gen4 SoCs common registers addresses have been added in header.

Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>

drivers/clock_control/CMakeLists.txt

@@ -71,6 +71,7 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_AGILEX5 clock_control_agilex5.
 if(CONFIG_CLOCK_CONTROL_RCAR_CPG_MSSR)
   zephyr_library_sources(clock_control_renesas_cpg_mssr.c)
   zephyr_library_sources_ifdef(CONFIG_DT_HAS_RENESAS_R8A7795_CPG_MSSR_ENABLED clock_control_r8a7795_cpg_mssr.c)
+  zephyr_library_sources_ifdef(CONFIG_DT_HAS_RENESAS_R8A779F0_CPG_MSSR_ENABLED clock_control_r8a779f0_cpg_mssr.c)
 endif()
 
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_AST10X0 clock_control_ast10x0.c)

drivers/clock_control/Kconfig.rcar

@@ -1,9 +1,9 @@
-# Copyright (c) 2021-2022 IoT.bzh
+# Copyright (c) 2021-2023 IoT.bzh
 # SPDX-License-Identifier: Apache-2.0
 
 config CLOCK_CONTROL_RCAR_CPG_MSSR
 	bool "RCar CPG MSSR driver"
 	default y
-	depends on DT_HAS_RENESAS_R8A7795_CPG_MSSR_ENABLED
+	depends on SOC_FAMILY_RCAR
 	help
 	  Enable support for Renesas RCar CPG MSSR driver.

drivers/clock_control/clock_control_r8a779f0_cpg_mssr.c

@@ -0,0 +1,186 @@
+/*
+ * Copyright (c) 2023 EPAM Systems
+ * Copyright (c) 2023 IoT.bzh
+ *
+ * r8a779f0 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT renesas_r8a779f0_cpg_mssr
+
+#include <errno.h>
+#include <zephyr/arch/cpu.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/clock_control/renesas_cpg_mssr.h>
+#include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
+#include <zephyr/dt-bindings/clock/r8a779f0_cpg_mssr.h>
+#include <zephyr/irq.h>
+#include "clock_control_renesas_cpg_mssr.h"
+
+#define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL
+#include <zephyr/logging/log.h>
+LOG_MODULE_DECLARE(clock_control_rcar);
+
+struct r8a779f0_cpg_mssr_cfg {
+	DEVICE_MMIO_ROM; /* Must be first */
+};
+
+struct r8a779f0_cpg_mssr_data {
+	struct rcar_cpg_mssr_data cmn; /* Must be first */
+};
+
+/* NOTE: the array MUST be sorted by module field */
+static struct cpg_clk_info_table core_props[] = {
+	RCAR_CORE_CLK_INFO_ITEM(R8A779F0_CLK_S0D12_PER, RCAR_CPG_NONE, RCAR_CPG_NONE,
+				RCAR_CPG_KHZ(66660)),
+
+	RCAR_CORE_CLK_INFO_ITEM(R8A779F0_CLK_CL16M, RCAR_CPG_NONE, RCAR_CPG_NONE,
+				RCAR_CPG_KHZ(16660)),
+};
+
+/* NOTE: the array MUST be sorted by module field */
+static struct cpg_clk_info_table mod_props[] = {
+	RCAR_MOD_CLK_INFO_ITEM(702, R8A779F0_CLK_S0D12_PER),
+	RCAR_MOD_CLK_INFO_ITEM(704, R8A779F0_CLK_S0D12_PER),
+
+	RCAR_MOD_CLK_INFO_ITEM(915, R8A779F0_CLK_CL16M),
+};
+
+static int r8a779f0_cpg_enable_disable_core(const struct device *dev,
+					    struct cpg_clk_info_table *clk_info, uint32_t enable)
+{
+	ARG_UNUSED(dev);
+	ARG_UNUSED(clk_info);
+	ARG_UNUSED(enable);
+
+	return -ENOTSUP;
+}
+
+static int r8a779f0_cpg_core_clock_endisable(const struct device *dev, struct rcar_cpg_clk *clk,
+					     bool enable)
+{
+	struct cpg_clk_info_table *clk_info;
+	struct r8a779f0_cpg_mssr_data *data = dev->data;
+	k_spinlock_key_t key;
+
+	clk_info = rcar_cpg_find_clk_info_by_module_id(dev, clk->domain, clk->module);
+	if (!clk_info) {
+		return -EINVAL;
+	}
+
+	if (enable) {
+		if (clk->rate > 0) {
+			int ret;
+			uintptr_t rate = clk->rate;
+
+			ret = rcar_cpg_set_rate(dev, (clock_control_subsys_t)clk,
+						(clock_control_subsys_rate_t)rate);
+			if (ret < 0) {
+				return ret;
+			}
+		}
+	}
+
+	key = k_spin_lock(&data->cmn.lock);
+	r8a779f0_cpg_enable_disable_core(dev, clk_info, enable);
+	k_spin_unlock(&data->cmn.lock, key);
+
+	return 0;
+}
+
+int r8a779f0_cpg_mssr_start_stop(const struct device *dev, clock_control_subsys_t sys, bool enable)
+{
+	struct rcar_cpg_clk *clk = (struct rcar_cpg_clk *)sys;
+	int ret;
+
+	if (!dev || !sys) {
+		return -EINVAL;
+	}
+
+	if (clk->domain == CPG_MOD) {
+		struct r8a779f0_cpg_mssr_data *data = dev->data;
+		k_spinlock_key_t key;
+
+		key = k_spin_lock(&data->cmn.lock);
+		ret = rcar_cpg_mstp_clock_endisable(DEVICE_MMIO_GET(dev), clk->module, enable);
+		k_spin_unlock(&data->cmn.lock, key);
+	} else if (clk->domain == CPG_CORE) {
+		ret = r8a779f0_cpg_core_clock_endisable(dev, clk, enable);
+	} else {
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static uint32_t r8a779f0_get_div_helper(uint32_t reg_val, uint32_t module)
+{
+	switch (module) {
+	case R8A779F0_CLK_S0D12_PER:
+	case R8A779F0_CLK_CL16M:
+		return 1;
+	default:
+		return RCAR_CPG_NONE;
+	}
+}
+
+static int r8a779f0_set_rate_helper(uint32_t module, uint32_t *divider, uint32_t *div_mask)
+{
+	ARG_UNUSED(module);
+	ARG_UNUSED(divider);
+	ARG_UNUSED(div_mask);
+
+	return -ENOTSUP;
+}
+
+static int r8a779f0_cpg_mssr_start(const struct device *dev, clock_control_subsys_t sys)
+{
+	return r8a779f0_cpg_mssr_start_stop(dev, sys, true);
+}
+
+static int r8a779f0_cpg_mssr_stop(const struct device *dev, clock_control_subsys_t sys)
+{
+	return r8a779f0_cpg_mssr_start_stop(dev, sys, false);
+}
+
+static int r8a779f0_cpg_mssr_init(const struct device *dev)
+{
+	DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
+
+	rcar_cpg_build_clock_relationship(dev);
+	rcar_cpg_update_all_in_out_freq(dev);
+	return 0;
+}
+
+static const struct clock_control_driver_api r8a779f0_cpg_mssr_api = {
+	.on = r8a779f0_cpg_mssr_start,
+	.off = r8a779f0_cpg_mssr_stop,
+	.get_rate = rcar_cpg_get_rate,
+	.set_rate = rcar_cpg_set_rate,
+};
+
+#define R8A779F0_MSSR_INIT(inst)							\
+	static struct r8a779f0_cpg_mssr_cfg cpg_mssr##inst##_cfg = {		\
+		DEVICE_MMIO_ROM_INIT(DT_DRV_INST(inst)),			\
+	};									\
+										\
+	static struct r8a779f0_cpg_mssr_data cpg_mssr##inst##_data = {		\
+		.cmn.clk_info_table[CPG_CORE] = core_props,			\
+		.cmn.clk_info_table_size[CPG_CORE] = ARRAY_SIZE(core_props),	\
+		.cmn.clk_info_table[CPG_MOD] = mod_props,			\
+		.cmn.clk_info_table_size[CPG_MOD] = ARRAY_SIZE(mod_props),	\
+		.cmn.get_div_helper = r8a779f0_get_div_helper,			\
+		.cmn.set_rate_helper = r8a779f0_set_rate_helper			\
+	};									\
+										\
+	DEVICE_DT_INST_DEFINE(inst,						\
+			      &r8a779f0_cpg_mssr_init,				\
+			      NULL,						\
+			      &cpg_mssr##inst##_data,				\
+			      &cpg_mssr##inst##_cfg,				\
+			      PRE_KERNEL_1,					\
+			      CONFIG_CLOCK_CONTROL_INIT_PRIORITY,		\
+			      &r8a779f0_cpg_mssr_api);
+
+DT_INST_FOREACH_STATUS_OKAY(R8A779F0_MSSR_INIT)

drivers/clock_control/clock_control_renesas_cpg_mssr.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022 IoT.bzh
+ * Copyright (c) 2022-2023 IoT.bzh
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -109,6 +109,34 @@ static const uint16_t srcr[] = {
 /* Peripherals Clocks */
 #define S3D4_CLK_RATE             66600000	/* SCIF	*/
 #define S0D12_CLK_RATE            66600000	/* PWM	*/
+#elif defined(CONFIG_SOC_SERIES_RCAR_GEN4)
+/* Software Reset Clearing Register offsets */
+#define SRSTCLR(i) (0x2C80 + (i) * 4)
+
+/* CPG write protect offset */
+#define CPGWPR      0x0
+
+/* Realtime Module Stop Control Register offsets */
+static const uint16_t mstpcr[] = {
+	0x2D00, 0x2D04, 0x2D08, 0x2D0C,
+	0x2D10, 0x2D14, 0x2D18, 0x2D1C,
+	0x2D20, 0x2D24, 0x2D28, 0x2D2C,
+	0x2D30, 0x2D34, 0x2D38, 0x2D3C,
+	0x2D40, 0x2D44, 0x2D48, 0x2D4C,
+	0x2D50, 0x2D54, 0x2D58, 0x2D5C,
+	0x2D60, 0x2D64, 0x2D68, 0x2D6C,
+};
+
+/* Software Reset Register offsets */
+static const uint16_t srcr[] = {
+	0x2C00, 0x2C04, 0x2C08, 0x2C0C,
+	0x2C10, 0x2C14, 0x2C18, 0x2C1C,
+	0x2C20, 0x2C24, 0x2C28, 0x2C2C,
+	0x2C30, 0x2C34, 0x2C38, 0x2C3C,
+	0x2C40, 0x2C44, 0x2C48, 0x2C4C,
+	0x2C50, 0x2C54, 0x2C58, 0x2C5C,
+	0x2C60, 0x2C64, 0x2C68, 0x2C6C,
+};
 #endif /* CONFIG_SOC_SERIES_RCAR_GEN3 */
 
 void rcar_cpg_write(uint32_t base_address, uint32_t reg, uint32_t val);

dts/bindings/clock/renesas,r8a779f0-cpg-mssr.yaml

@@ -0,0 +1,8 @@
+# Copyright (c) 2023 EPAM Systems
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas R8A779F0 SoC Clock Pulse Generator / Module Standby and Software Reset
+
+compatible: "renesas,r8a779f0-cpg-mssr"
+
+include: renesas,rcar-cpg-mssr.yaml

include/zephyr/dt-bindings/clock/r8a779f0_cpg_mssr.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2023 IoT.bzh
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A779F0_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A779F0_H_
+
+#include "renesas_cpg_mssr.h"
+
+/* r8a779f0 CPG Core Clocks */
+#define R8A779F0_CLK_Z0			0
+#define R8A779F0_CLK_Z1			1
+#define R8A779F0_CLK_ZR			2
+#define R8A779F0_CLK_ZX			3
+#define R8A779F0_CLK_ZS			4
+#define R8A779F0_CLK_ZT			5
+#define R8A779F0_CLK_ZTR		6
+#define R8A779F0_CLK_S0D2		7
+#define R8A779F0_CLK_S0D3		8
+#define R8A779F0_CLK_S0D4		9
+#define R8A779F0_CLK_S0D2_MM		10
+#define R8A779F0_CLK_S0D3_MM		11
+#define R8A779F0_CLK_S0D4_MM		12
+#define R8A779F0_CLK_S0D2_RT		13
+#define R8A779F0_CLK_S0D3_RT		14
+#define R8A779F0_CLK_S0D4_RT		15
+#define R8A779F0_CLK_S0D6_RT		16
+#define R8A779F0_CLK_S0D3_PER		17
+#define R8A779F0_CLK_S0D6_PER		18
+#define R8A779F0_CLK_S0D12_PER		19
+#define R8A779F0_CLK_S0D24_PER		20
+#define R8A779F0_CLK_S0D2_HSC		21
+#define R8A779F0_CLK_S0D3_HSC		22
+#define R8A779F0_CLK_S0D4_HSC		23
+#define R8A779F0_CLK_S0D6_HSC		24
+#define R8A779F0_CLK_S0D12_HSC		25
+#define R8A779F0_CLK_S0D2_CC		26
+#define R8A779F0_CLK_CL			27
+#define R8A779F0_CLK_CL16M		28
+#define R8A779F0_CLK_CL16M_MM		29
+#define R8A779F0_CLK_CL16M_RT		30
+#define R8A779F0_CLK_CL16M_PER		31
+#define R8A779F0_CLK_CL16M_HSC		32
+#define R8A779F0_CLK_ZB3		33
+#define R8A779F0_CLK_ZB3D2		34
+#define R8A779F0_CLK_ZB3D4		35
+#define R8A779F0_CLK_SD0H		36
+#define R8A779F0_CLK_SD0		37
+#define R8A779F0_CLK_RPC		38
+#define R8A779F0_CLK_RPCD2		39
+#define R8A779F0_CLK_MSO		40
+#define R8A779F0_CLK_POST		41
+#define R8A779F0_CLK_POST2		42
+#define R8A779F0_CLK_SASYNCRT		43
+#define R8A779F0_CLK_SASYNCPERD1	44
+#define R8A779F0_CLK_SASYNCPERD2	45
+#define R8A779F0_CLK_SASYNCPERD4	46
+#define R8A779F0_CLK_DBGSOC_HSC		47
+#define R8A779F0_CLK_RSW2		48
+#define R8A779F0_CLK_CPEX		49
+#define R8A779F0_CLK_CBFUSA		50
+#define R8A779F0_CLK_R			51
+#define R8A779F0_CLK_OSC		52
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_CLOCK_R8A779F0_H_ */